HIP6019B_05 INTERSIL [Intersil Corporation], HIP6019B_05 Datasheet - Page 12

• Manufacturer Part Number: HIP6019B_05
• Description: Advanced Dual PWM and Dual Linear Power Control
• Manufacturer: INTERSIL [Intersil Corporation]

be programmed close to each other, then cross-talk could
cause nonuniform PHASE pulse-widths and increased output
voltage ripple. The HIP6019B avoids this problem by
synchronizing the two converters 180
settings above, and including 2.5V. This is accomplished by
inverting the triangle wave sent to PWM 2.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output
capacitor to filter the current ripple. The linear regulator is
internally compensated and requires an output capacitor that
meets the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and ESL (effective
series inductance) parameters rather than actual capacitance.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the equivalent series inductance of these capacitors
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately,
ESL is not a specified parameter. Work with your capacitor
supplier and measure the capacitor’s impedance with
frequency to select suitable components. In most cases,
multiple electrolytic capacitors of small case size perform
better than a single large case capacitor. For a given transient
load magnitude, the output voltage transient response due to
the output capacitor characteristics can be approximated by
the following equation:
Linear Output Capacitors
V
TRAN
=
ESL
×
dI
-------------------- -
TRAN
dt
+
ESR
12
×
I
TRAN
o
out-of-phase for DAC
HIP6019B
The output capacitors for the linear regulator and the linear
controller provide dynamic load current. The linear controller
uses dominant pole compensation integrated in the error
amplifier and is insensitive to output capacitor selection.
Capacitor, C
regulation.
The output capacitor for the linear regulator provides loop
stability. The linear regulator (OUT4) requires an output
capacitor characteristic shown in Figure 13 The upper line
plots the 45 phase margin with 150mA load and the lower
line is the 45 phase margin limit with a 10mA load. Select a
C
Output Inductor Selection
Each PWM converter requires an output inductor. The
output inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6019B will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitors. Minimizing the response time can minimize the
output capacitance required.
∆I
OUT4
=
0.7
0.6
0.5
0.4
0.3
0.2
0.1
V
------------------------------- -
10
IN
F
capacitor with characteristic between the two limits.
S
–
×
FIGURE 13.
V
OUT3
L
OUT
O
×
should be selected for transient load
V
--------------- -
V
OUT
IN
C
OUT4
CAPACITANCE (µF)
OUTPUT CAPACITOR
100
∆V
OUT
=
∆I
×
ESR
April 13, 2005
FN4587.1
1000