TLE5012-E0742 INFINEON [Infineon Technologies AG], TLE5012-E0742 Datasheet - Page 32

• Manufacturer Part Number: TLE5012-E0742
• Description: GMR-Based Angular Sensor for Rotor-Position Sensing
• Manufacturer: INFINEON [Infineon Technologies AG]

Data Communication via SSC
Figure 20
The data communication via SSC Interface has the following characteristics:
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Cyclic Redundancy Check (CRC)
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Figure 21
Final Data Sheet
output
Serial
CRC
DATA
SCK
CSQ
The data transmission order is “Most Significant Bit (MSB) first”.
Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.
The SSC Interface is word-aligned. All functions are activated after each transmitted word.
A “high” condition on the negated Chip Select pin (CSQ) of the selected TLE5012 interrupts the transfer
After changing the data direction, a delay (t
With ND = 0, no auto-increment is done and a continuously readout of the same address can occur. Afterwards
After every data transfer with ND ≥ 1, the 16-bit Safety Word will be appended by the selected TLE5012.
After the Safety Word is sent, the transfer ends. To start another data transfer, the CSQ has to be deselected
The SSC is by default push-pull. The push-pull driver is active only if the TLE5012 has to send data; otherwise
The remainder of the fast CRC circuit is initial set to ’11111111
The remainder is inverted before transmission.
immediately. The CRC calculator is automatically reset.
necessary for internal register access.
Every access to the TLE5012 with the number of data (ND) ≥ 1 is performed with address auto-increment. At
an overflow at address 3F
no Safety Word is sent and the transfer ends with high condition on CSQ.
once for t
the push-pull is disabled for receiving data from the microcontroller.
This CRC complies with the J1850 Bus Specification.
Every new transfer resets the CRC generation.
Every byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).
Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast CRC generation circuit is used
(see
Figure
RW
MSB
Fast CRC polynomial division circuit
SSC bit ordering (read example)
CSoff
X7
SSC Transfer
21)
SSC -Master is driving DAT A
SSC -Slave is driving DAT A
.
1
14
X6
13
LOCK
1
Command Word
12
X5
H
the transfer continuous at address 00
1
11
X4
UPD
10
1
9
Remainder
xor
parallel
wr_delay
8
X3
1
7
ADDR
) has to occur before continuing the data transfer. This is
32
6
xor
X2
5
1
B
4
’.
H
.
xor
3
X1
LENGTH
2
1
X0
1
1
LSB
t
wr_delay
MSB
&
Specifications
xor
V 1.0, 2010-11
1
Data Word (s)
TLE5012
LSB
TX_CRC
Input