LM96080CIMT-NOPB1 NSC [National Semiconductor], LM96080CIMT-NOPB1 Datasheet - Page 25

• Manufacturer Part Number: LM96080CIMT-NOPB1
• Description: System Hardware Monitor with 2-Wire Serial Interface
• Manufacturer: NSC [National Semiconductor]

Bit
0
1
2
3
4
5
6
7
12.7 Interrupt Mask Register 2—Address 04h
Power on default <7:0> = 0000 0000 binary
Hot Temperature
BTI
FAN1
FAN2
GPI (Chassis
Intrusion)
OS bit
Hot Temperature
Interrupt Mode
Select
OS Bit Interrupt
Mode Select
Name
Read/Write A one disables the corresponding interrupt status bit for INT interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT interrupt.
Read/Write A one disables the corresponding interrupt status bit for INT interrupt.
Read/Write A zero selects the default interrupt mode which gives the user an interrupt if the temperature
Read/Write A zero selects the default interrupt mode which gives the user an interrupt if the temperature
Read/Write
goes above the hot limit. The interrupt will be cleared once the status register is read, but it will
again be generated when the next conversion has completed. It will continue to do so until the
temperature goes below the hysteresis limit.
A one selects the one time interrupt mode which only gives the user one interrupt when it goes
above the hot limit. The interrupt will be cleared once the status register is read. Another in-
terrupt will not be generated until the temperature goes below the hysteresis limit. It will also
be cleared if the status register is read. No more interrupts will be generated until the temper-
ature goes above the hot limit again. The corresponding bit will be cleared in the status register
every time it is read but may not set again when the next conversion is done. (Refer to the
Temperature Interrupt Response Diagram in Section 8.2).
goes above the OS limit. The interrupt will be cleared once the status register is read, but it will
again be generated when the next conversion has completed. It will continue to do so until the
temperature goes below the hysteresis limit.
A one selects the one time interrupt mode which only gives the user one interrupt when it goes
above the OS limit. The interrupt will be cleared once the status register is read. Another in-
terrupt will not be generated until the temperature goes below the hysteresis limit. It will also
be cleared if the status register is read. No more interrupts will be generated until the temper-
ature goes above the OS limit again. The corresponding bit will be cleared in the status register
every time it is read but may not set again when the next conversion is done. (Refer to the
Temperature Interrupt Response Diagram in Section 8.2).
25
Description
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