LX64BCF1003 LATTICE [Lattice Semiconductor], LX64BCF1003 Datasheet - Page 19
![no-image](/images/no-image-200.jpg)
LX64BCF1003
Manufacturer Part Number
LX64BCF1003
Description
High Performance Interfacing and Switching
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.LX64BCF1003.pdf
(72 pages)
- Current page: 19 of 72
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Lattice Semiconductor
Figure 15. Operation in SERDES Only Mode
Notes:
1. Some pins shared. See Logic Signal
Connections table for details.
2. For SERDES only mode programmable bit
holds FIFO in reset. Input registers used for
DOUT, and RECCLK configured as
latches and held in pass through.
GRP
Output
Output
Output
Latch
Latch
Latch
Latch
Latch
Latch
Input
Reg/
Reg/
Input
Reg/
Input
Reg/
Reg/
Reg/
GDX Block
Delay
1, 2
EMPTY
DOUT
RCLK
RE
FULL
FIFORSTb
FIFO
WCLK
19
WE
DIN
PT-CLK/CE(0:3)
GCLK/CE(0:3)
10
10
SYDT
Parallel
Parallel
RECCLK
RXD
Data
Data
TXD
POR
RESETb
SERDES
ispGDX2 Family Data Sheet
CDRRSTb
Serial
Data Out
(SOUT)
Serial
Data In
(SIN)
Pre-Assigned Pins
CAL
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