LX64BCF1003 LATTICE [Lattice Semiconductor], LX64BCF1003 Datasheet - Page 7

• Manufacturer Part Number: LX64BCF1003
• Description: High Performance Interfacing and Switching
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 4. ispGDX2 Family Control Array
sysIO Banks
The inputs and outputs of ispGDX2 devices are divided into eight sysIO banks, where each bank is capable of sup-
porting different I/O standards. The number of I/Os per bank is 32, 16 and 8 for the 256-, 128- and 64-I/O devices
respectively. Each sysIO bank has its own I/O supply voltage (V
bank complete independence from the other banks. Each I/O within a bank can be individually configured to any
standard consistent with the V
The I/O of the ispGDX2 devices contain a programmable strength and slew rate tri-state output buffer, a program-
mable input buffer, a programmable pull-up resistor, a programmable pull-down resistor and a programmable bus-
keeper latch. These programmable capabilities allow the support of a wide range of I/O standards.
32 Inputs from Control GRP
CCO
and V
REF
settings. Figure 5 shows the I/O banks for the ispGDX2-256 device.
7
CCO
) and reference voltage (V
Each connection
is programmable.
ispGDX2 Family Data Sheet
MUX Select
to Nibble 0
MUX Select
to Nibble 1
MUX Select
to Nibble 2
MUX Select
to Nibble 3
To MRB Clock/
Clock Enable
To MRB
Set/Reset
To MRB
Output Enable
On selected blocks,
this signal can reset
the M Divider of the
PLL.
REF
), allowing each