SC410 SEMTECH [Semtech Corporation], SC410 Datasheet - Page 16

• Manufacturer Part Number: SC410
• Description: 3A EcoSpeed TM Step-Down Regulator with LDO and Ultrasonic Power Save
• Manufacturer: SEMTECH [Semtech Corporation]

Applications Information (continued)
PGOOD will transition low if the V
nominal, which is also the over-voltage shutdown thresh-
old (900mV).
Output Over-Voltage Protection
OVP (Over-Voltage Protection) becomes active as soon as
the device is enabled. The threshold is set at 750mV + 20%
(900mV). When V
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off , until the EN input is
toggled or V
OVP detector to prevent false transitions. PGOOD is also
low after an OVP event.
Output Under-Voltage Protection
When V
562.5mV) for eight consecutive clock cycles, the switcher
is shut off and the DH and DL drives are pulled low to turn
off the MOSFETs. The controller stays off until EN is toggled
or V
Over-Temperature Protection
If the temperature rises to 145°C the device will latch off .
The device can be activated after the temperature is
reduced below 145°C by cycling the EN pin.
V
UVLO (Under-Voltage Lock-Out) circuitry inhibits switch-
ing and tri-states the power FETs until V
4.0V. An internal POR (Power-On Reset) occurs when V
exceeds 4.0V, which resets the fault latch and soft start
counter to begin the soft start cycle. The SC410 then
begins a soft start cycle. The PWM will shut off if V
below 3.7V.
Internal LDO Regulator
The SC410 has an internal regulator that supplies the bias
voltage for the PWM controller. This LDO can also supply
an additional external current for an external load through
the LDO pin.
When activated, the LDO checks the status of the
following signals to ensure proper operation can be
maintained.
1.
2.
3.
LDO
IN
EN pin
V
VIN input voltage
UVLO, and POR
LDO
is cycled.
FB
output voltage
falls to 75% of its nominal voltage (falls to
IN
is cycled. There is a 5μs delay built into the
FB
exceeds the OVP threshold, DL latches
FB
pin exceeds +20% of
LDO
rises above
LDO
falls
LDO
While the EN pin is above 0.5V, the LDO will be activated.
While the V
the fi nal LDO voltage), the LDO short-cicuit protection is
enabled and limits the current to about 35mA. After the
V
regulation mode where the current is limited to about
100mA.
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specifi ed.
The maximum input voltage (V
fi ed input voltage. The minimum input voltage ( V
determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters defi ne the design.
The two values of load current to evaluate are continuous
load current and peak load current. Continuous load
current relates to thermal stresses which drive the selec-
tion of the inductor and input capacitors. Peak load current
determines instantaneous component stresses and fi lter-
ing requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
80% of V
LDO
•
•
•
•
exceeds 4.0V, then the LDO operates in its normal
V
Nominal output voltage (V
Static or DC output tolerance
Transient response
Maximum load current (I
LDO
LDO
Final
Final
LDO
output voltage remains below 4V (80% of
Figure 8 — LDO Start-Up
Sort-circuit Protection @ ~35mA
OUT
INMAX
OUT
)
)
) is the highest speci-
Voltage regulating with
~100mA current limit
SC410
INMIN
) is
16