CS5212GD14 ONSEMI [ON Semiconductor], CS5212GD14 Datasheet - Page 11

• Manufacturer Part Number: CS5212GD14
• Description: Low Voltage Synchronous Buck Controller
• Manufacturer: ONSEMI [ON Semiconductor]

V
amount of output ripple must be fed back to the V
typically 50 mV. For most application, this requirement is
simple to achieve and the V
the V
stringent load transient requirements. One of the key factor in
achieving tight dynamic voltage regulation is low ESR. Low
ESR at the regulator output results in low output voltage
ripple. This situation could result in increase noise sensitivity
and a potential for loop instability. In applications where the
output ripple is not sufficient, the performance of the CS5212
can be improved by adding a fixed amount external ramp
compensation to the V
of ramp at the V
Feedback Voltage, R1 and C2.
where:
large, typically 100 k or larger. With R1 chosen, C2 can be
determined by the following;
equal to or greater than C2.
Maximum Frequency Operation
operating frequency. The duty factor, given by the
output/input voltage ratio, multiplied by the period
determines the pulse width during normal operation. This
pulse width must be greater than 200 ns, or duty cycle jitter
could become excessive. For low pulse widths below 300 ns,
external slope compensation should be added to the V
to increase the PWM ramp signal and improve stability.
50 mV of added ramp at the V
Figure 7. Small RC Filter Providing the Proper Voltage
FFB
To take full advantage of the V
Vramp = amount of ramp needed;
Vsw = switch note voltage;
V
ton = switch on−time.
To minimize the lost in efficiency R1 resistance should be
C1 is used as a bypass capacitor and its value should be
The minimum pulse width may limit the maximum
FB
Ramp at the Beginning of Each On−Time Cycle
Feedback Selection
FB
= voltage feedback, 1 V;
Vramp + (Vsw * V FB )
C2 + (Vsw * V FB )
pin. There are some application that have to meet
FFB
C1
C2
R1
Vsw
pin depends on the switch node Voltage,
FFB
pin. Refer to Figure 7, the amount
FFB
FFB
R2
1.0 k
can be connected directly to
ton (R1
2
pin is typically enough.
ton (R1
control scheme, a small
V
V
FFB
FB
Vramp)
C2)
FFB
FFB
http://onsemi.com
pin,
pin
11
Current Sense Component Selection
voltage differential between the IS+ and IS− pins. Referring
to Figure 8, the time constant of the R2,C1 filter should be set
larger than the L/R1 time constant under worst case
tolerances, to prevent overshoot in the sensed voltage and
tripping the current limit too low. Resistor R3 of value equal
to R2 is added for bias current cancellation. R2 and R3 should
not be made too large, to reduce errors from bias current
offsets. For typical L/R time constants, a 0.1 mF capacitor for
C1 will allow R2 to be between 1.0 k and 10 kW.
is given by 60 mV/R1, where R1 is the internal resistance of
the inductor, obtained from the manufacturer. The addition of
R5 can be used to decrease the current limit to a value given
by:
where V
current limit to a value given by:
inductor voltage drop which corresponds to 60 mV at the IS+
and IS− pins.
Boost Component Selection for Upper and Lower
FET Gate Drive
voltage to drive the upper FET. This voltage may be provided
by a fixed higher voltage or it may be generated with a boost
capacitor and charging diodes, as shown in Figure 1. The
voltage in the boost configuration would be the summation of
the voltage from the charging diodes and the output voltage
swing. Care must be taken to keep the peak voltage with
respect to ground less than 20 V peak. The capacitor value
should be ten times larger than the capacitance of the top FET.
The boost circuit requires a modification to achieve startup.
See Rpullup Selection for boost circuit startup.
The current limit threshold is set by sensing a 60 mV
The current limit without R4 and R5, which are optional,
Similiarly, omitting R5 and adding R4 will increase the
Essentially, R4 or R5 are used to increase or decrease the
The boost (BST) pin provides for application of a higher
I LIM + (60 mV * (V OUT
IS−
IS+
Switching
Node
OUT
60 mV Trip
I LIM + 60 mV R1
is the output voltage.
Figure 8. Current Limit
L1
R2
L
R5
R1
(1 ) R2 R4)
R3 (R3 ) R5)) R1
C1
R4
R3
V
OUT