A8287 ALLEGRO [Allegro MicroSystems], A8287 Datasheet - Page 8

• Manufacturer Part Number: A8287
• Description: LNB Supply and Control Voltage Regulator
• Manufacturer: ALLEGRO [Allegro MicroSystems]

Timing Considerations
The control sequence of the communication through the I
interface is composed of several steps in sequence:
Except to indicate a Start or Stop condition, SDA must be
stable while the clock is high. SDA can only be changed
while SCL is low. It is possible for the Start or Stop condition
1. Start Condition. Defi ned by a negative edge on the SDA
2. Address Cycle. 7 bits of address, plus 1 bit to indicate
3. Data Cycles. 8 bits of data followed by an acknowledge
4. Stop Condition. Defi ned by a positive edge on the SDA
line, while SCL is high.
read (1) or write (0), and an acknowledge bit. The fi rst
fi ve bits of the address are fi xed as: 00010. The four
optional addresses, defi ned by the remaining two bits, are
selected by the ADD input. The address is transmitted
MSB fi rst.
bit. Multiple data bytes can be read. Data is transmitted
MSB fi rst.
line, while SCL is high.
Reading One Byte from the Register
Writing to the Register
Reading Multiple Bytes from the Register
SDA
SCL
Start
0
1
0
2
SDA
SDA
SCL
SCL
0
3
Start
Start
Address
1
4
0
1
0
1
0
5
A1
0
2
0
2
6
A0
0
3
0
3
7
Address
Address
R
1
4
1
4
1
8
AK
0
5
0
5
9
acknowledge
from LNBR
Application Information
A1
A1
D7
6
6
A0
A0
D6
7
7
LNB Supply and Control Voltage Regulator
www.allegromicro.com
D5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
W
R
0
8
1
8
Status Data
2
AK
AK
D4
9
C
9
acknowledge
from LNBR
acknowledge
from LNBR
D7
D7
D3
to occur at any time during a data transfer. The A8285/A8287
always responds by resetting the data transfer sequence.
The Read/Write bit is used to determine the data transfer
direction. If the Read/Write bit is high, the master reads one
or more bytes from the A8285/A8287. If the Read/Write bit
is low, the master writes one byte to the A8285/A8287. Note
that multiple writes are not permitted. All write operations
must be preceded with the address.
The Acknowledge bit has two functions. It is used by the
master to determine if the slave device is responding to its
address and data, and it is used by the slave when the master
is reading data back from the slave. When the A8285/A8287
decodes the 7-bit address fi eld as a valid address, it responds
by pulling SDA low during the ninth clock cycle.
During a data write from the master, the A8285/A8287 also
pulls SDA low during the clock cycle that follows the data
byte, in order to indicate that the data has been successfully
received. In both cases, the master device must release the
D6
D6
D2
D5
D5
D1
Control Data
Status Data
D4
D4
D0
D3
D3
AK
acknowledge
from master
D2
D2
D7
D1
D1
D6
D0
D0
D5
Status Data
NAK
AK
D4
acknowledge
from LNBR
no acknowledge
from master
Stop
Stop
D3
A8285/A8287
D2
D1
D0
NAK
no acknowledge
from master
Stop
8