LT3825EFE-PBF LINER [Linear Technology], LT3825EFE-PBF Datasheet - Page 6

• Manufacturer Part Number: LT3825EFE-PBF
• Description: Isolated No-Opto Synchronous Flyback Controller with Wide Input Supply Range
• Manufacturer: LINER [Linear Technology]

LT3825
TYPICAL PERFORMANCE CHARACTERISTICS
SG (Pin 1): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchro-
nous switch. Large dynamic currents may fl ow during
voltage transitions. See the Applications Information for
details.
V
ground with a 4.7μF capacitor or more. This pin has a
19.5V clamp to ground. V
function that turns the part on when V
15.3V and off at 9.7V. In a conventional “trickle-charge”
bootstrapped confi guration, the V
increases signifi cantly during turn-on causing a benign
relaxation oscillation action on the V
not start normally.
t
the minimum time that the primary switch is on for each
cycle. Minimum turn-on facilitates the isolated feedback
method. See Applications Information for details.
ENDLY (Pin 4): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifi er for a fi xed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for fl yback voltage sensing.
See Applications Information for details.
PIN FUNCTIONS
6
ON
CC
340
330
320
310
300
290
280
270
260
(Pin 3): Pin for external programming resistor to set
(Pin 2): Supply Voltage Pin. Bypass this pin to
–50
Minimum PG On Time
vs Temperature
R
tON(MIN)
–25
= 158k
0
TEMPERATURE (°C)
25
50
CC
75
has an undervoltage lockout
100
3825 G19
125
CC
CC
CC
pin if the part does
is approximately
supply current
200
100
300
250
150
50
0
–50
PG Delay Time vs Temperature
–25
0
TEMPERATURE (°C)
R
R
25
PGDLY
PGDLY
SYNC (Pin 5): Pin for synchronizing the internal oscilla-
tor with an external clock. The positive edge on a pulse
causes the oscillator to discharge causing PG to go low
(off) and SG high (on). The sync threshold is typically 1.6V.
See Applications Information for details. Tie to ground if
unused.
SFST (Pin 6): This pin, in conjunction with a capacitor to
ground, controls the ramp-up of peak primary current as
sensed through the sense resistor. This is used to control
converter inrush current at start-up. The V
cannot exceed the SFST pin voltage, so as SFST increases,
the maximum voltage on V
allowing higher peak currents. Total V
proximately 70ms per μF of capacitance. Leave pin open
if not using the soft-start function.
OSC (Pin 7): This pin in conjunction with an external
capacitor defi nes the controller oscillator frequency. The
frequency is approximately 100kHz • 100/C
FB (Pin 8): Pin for the feedback node for the power sup-
ply feedback amplifi er. Feedback is usually sensed via
a third winding and enabled during the fl yback period.
This pin also sinks additional current to compensate for
load current variation as set by the R
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
50
= 27.4k
= 16.9k
75
100
3825 G20
125
260
240
140
220
200
180
160
–50
Enable Delay Time vs Temperature
R
C
ENDLY
–25
increases commensurately,
= 90k
0
TEMPERATURE (°C)
25
C
CMP
ramp time is ap-
50
pin. Keep the
C
OSC
pin voltage
75
(pF).
100
3825 G21
3525fa
125