TSI-1 AGERE [Agere Systems], TSI-1 Datasheet - Page 28
TSI-1
Manufacturer Part Number
TSI-1
Description
1k x 1k Time-Slot Interchanger
Manufacturer
AGERE [Agere Systems]
Datasheet
1.TSI-1.pdf
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TSI-1
1k x 1k Time-Slot Interchanger
Table 5-6. Microprocessor Port Timing—Read Cycle
28
28
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DATA[15:0]
ADDR[15:0]
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PAR[1:0]
MPUCLK
R/W
DT
CS
AS
Address Setup
Address Hold
Chip Select Setup
Chip Select Hold
Address Strobe Setup
Address Strobe Hold
R/W Setup
R/W Hold
Data Output Enable
Data Clock to Valid
Data High Impedance
DT High Impedance to Valid
DT Clock to Out
DT Valid to High Impedance
Figure 5-16. Microprocessor Port Timing—Read Cycle
t
t
t
t
t
34
23
27
29
25
t
t
24
28
Description
t
31
t
35
t
32
Min
—
—
5
1
5
1
5
1
5
1
1
1
1
1
Data Sheet, Revision 3
September 21, 2005
t
t
t
26
30
35
Max
15
15
—
—
—
—
—
—
—
—
7
8
7
8
Agere Systems Inc.
t
33
t
36
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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