TSI-8 AGERE [Agere Systems], TSI-8 Datasheet
TSI-8
Related parts for TSI-8
TSI-8 Summary of contents
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... Ball de- scriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are 25. included. 1.1 Related Documents More information on the TSI-8 is contained in the following documents: TSI-8 Product Description ® , TSI-8 Register Description TSI-8 Systems Design Guide ...
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... TSI Time-Slot Interchanger Contents 1 Introduction .............................................................. 1 1.1 Related Documents .......................................... 1 2 Description ............................................................... 1 2.1 Block Diagram and High-Level Interface Definition .......................................................... 1 3 Ball Information ........................................................ 3 3.1 Ball Diagram ..................................................... 3 3.2 Package Ball Assignments ............................... 4 3.3 Ball Types ......................................................... 8 3.4 Ball Definitions .................................................. 8 4 Absolute Maximum Ratings ................................... 11 4.1 Handling Precautions ..................................... 11 4.2 ESD Tolerance ............................................... 11 4.3 Package Thermal Characteristics ................... 11 4.4 Recommended Operating Conditions ............ Electrical Characteristics ...
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... Hardware Design Guide, Revision 1 November 2, 2005 3 Ball Information 3.1 Ball Diagram The TSI-8 is housed in a 240-ball plastic ball grid array. Figure 3-1 shows the ball arrangement viewed from the top of the package. The balls are spaced on a 1.0 mm pitch ...
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... TSI Time-Slot Interchanger 3.2 Package Ball Assignments Table 3-1. Package Ball Assignments in Signal Name Order Symbol Ball Symbol ADDR00 A17 DATA13 ADDR01 A16 DATA14 ADDR02 A15 DATA15 ADDR03 A14 DT ADDR04 A13 FSYNC ADDR05 A12 HIZ ADDR06 A11 INT ADDR07 A10 MPUCLK ADDR08 ...
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... Time-Slot Interchanger Ball Symbol Ball J10 J11 J15 R10 R15 K10 V T12 SS K11 V T13 T16 U17 SS L10 V U18 SS L11 L15 V V18 R13 SSPLL N4 P4 TSI-8 5 ...
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... TSI Time-Slot Interchanger Table 3-2. Package Ball Assignments in Ball Number Order (Top View) (continued VSS ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR09 ADDR08 ADDR07 ADDR06 ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 ADDR00 B TXD00 VSS VSS VSS VSS C TXD02 TXD01 ...
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November 2, 2005 Table 3-3. Package Ball Assignments in Ball Number Order (Bottom View VSS ADDR00 ADDR01 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 VSS B RSV7 VSS ...
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... TSI Time-Slot Interchanger 3.3 Ball Types This table describes each type of input, output, and I/O ball used on the TSI-8. Table 3-4. Ball Types Type Label I CMOS input, TTL switching thresholds CMOS input, TTL switching thresholds with internal pull-down resistor CMOS input, TTL switching thresholds with internal pull-up resistor. ...
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... Required for operation. 200 kΩ pull-up resistor. Note: The TSI-8 is little-endian; the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. Care must be exercised in connection to microprocessors that use big-endian byte ordering ...
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... TSI Time-Slot Interchanger Table 3-9. Power Balls Symbol Type V P I/O Power. Power supply balls for the I/O pads (3.3 V ± 5%). DD33 V P Core Power. Power supply balls for the core (1.5 V ± 5%). DD15 V P Ground. Common ground balls for 3.3 V and 1.5 V supplies Precharge. Precharge voltage to support H.110 hot insertion on TXD[31:00]. If the device is used in an PRE H.110 hot insertion applications, the signal should be connected to backplane early voltage ...
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... MHz, CHICLK = 16.384 MHz °C, all CHIs active, all outputs loaded with 50 pF. Agere Systems Inc Time-Slot Interchanger Min –0.5 –0.5 –0.5 –0.3 –40 — Voltage 2,000 V 500 V * Typ 100 mW at 3.3 V 275 mW at 1.5 V TSI-8 Max Unit 4.2 V 1 0.3 DD33 125 °C 125 °C Type ...
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... TSI Time-Slot Interchanger 4.4 Recommended Operating Conditions Recommended conditions apply unless otherwise specified. Table 4-4. Operating Conditions Parameter Supply Voltage (V ) DD33 Supply Voltage (V ) DD15 Ambient Temperature 12 12 Hardware Design Guide, Revision 1 Min Typ 3.14 3.3 1.4 1.5 –40 — November 2, 2005 Max Unit 3. °C Agere Systems Inc. ...
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... Hardware Design Guide, Revision 1 November 2, 2005 5 dc Electrical Characteristics This section describes the static parameters associated with all the ball types used in the TSI-8 device. Table 5-1. CMOS Inputs Parameter Input Leakage Current High-Input Voltage Low-Input Voltage Input Capacitance * Excludes current due to pull-up or pull-down resistors. ...
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... TSI Time-Slot Interchanger 6 Timing Diagrams and ac Characteristics Figure 6-1 and Figure 6-2 describe the timing specifications for the input clocks on the TSI- Table 6-1. CHICLK Timing Specifications Parameter Description t CHICLK Rise Time 1 t CHICLK Width (8.192 MHz CHICLK Width (16.384 MHz)* ...
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... CHICLK RXD t 17 TXD Note: This figure assumes TSI-8 is programmed to sample FSYNC on rising edge of CHICLK. Table 6-4. CHI Interface Timing Parameter t FSYNC Setup Time to Active CHICLK Edge 13 t FSYNC Hold Time from Active CHICLK Edge 14 t RXD Setup to Active CHICLK Edge ...
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... TSI Time-Slot Interchanger All timing specifications also apply under the following conditions active-low. If the falling edge of CHICLK is specified as the active edge. At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of 16.384 MHz or 8.192 MHz. ...
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... TS0 B3 TS0 B4 TS0 B2 TS0 B3 TS0 B2 TS0 B3 TS0 B2 TS0 B3 TS0 B1 TS0 B2 TS0 B3 TS0 B0 TS0 B1 TS127 B3 TS127 B4 TS127 B5 TS127 B2 TS127 B3 TS127 B4 TS114 B7 TS115 B0 TS0 B3 TS0 B4 TS0 B2 TS0 B3 TS0 B1 TS0 B2 TS0 B3 TS0 B1 TS0 B2 TS0 B1 TS0 B2 TS127 B2 TS127 B3 TS0 B2 TS0 B3 TSI-8 TS0 B4 TS115 B1 TS0 B3 17 ...
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... TSI Time-Slot Interchanger FSYNC CHICLK w/ 0 offset w/ ¼ bit offset TS63 B7 w/ ½ bit offset TS63 B7 w/ ¾ bit offset TS63 B7 w/ bit offset = 1 w/ 2¾ bit offset TS63 B5 w/ bit offset = offset = 1, bit offset = offset = 13, TS50 B4 bit offset = 3¼ ...
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... TS31 B7 TS31 B7 TS0 Time-Slot Interchanger TS0 B1 TS0 B1 TS0 B1 data sampled TS0 B0 data sampled TS0 B0 TS31 B6 data sampled TS31 B2 TS31 B1 TS18 B6 TS0 B1 data sampled TS0 B0 TS0 B0 TS0 B0 TS31 B7 TS31 B0 TS0 B1 TSI-8 TS0 TS31 TS0 TS0 B1 TS0 B0 TS31 B01 19 ...
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... TSI Time-Slot Interchanger FSYNC CHICLK w/ 0 offset TS127 B6 w/ ¼ bit offset TS127 B6 w/ ½ bit offset TS127 B6 w/ ¾ bit offset TS127 B5 TS127 B6 w/ bit offset = 1 TS127 B5 w/ 2¾ bit offset TS127 B3 TS127 B4 w/ bit offset = 7 TS126 offset = 1, ...
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... Mbits/s Table 6-5. CHI 3-State Output Control Control in the table below refers to bits [6:4] in the Transmit_CHI_Global_Configuration register (0x0C84). This only applies if bits 13 and 12 of the corresponding Transmit_CHI_Control register (0x0C00—0x0C3E) are set to 11. See the TSI-8 Reg- ister Description document. Parameter Control ...
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... TSI Time-Slot Interchanger MPUCLK t ADDR[15:00 R/W DATA[15:00] PAR[1: Figure 6-16. Microprocessor Port Timing—Read Cycle Table 6-6. Microprocessor Port Timing—Read Cycle Parameter t Address Setup 23 Address Hold t 24 Chip Select Setup t 25 Chip Select Hold t 26 Address Strobe Setup t 27 ...
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... DT Valid to High-Impedance t 49 Note: Posted writes follow the same timing shown in Figure 6-17 and Table 6-7. A posted write may return a DT prior to the device completing the write cycle. This allows the microprocessor to continue operation while the TSI-8 completes the write. Agere Systems Inc. 37 ...
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... TSI Time-Slot Interchanger 7 Outline Diagrams Dimensions are in millimeters. A1 INDICATOR (PLATED) 0.80 ± 0.050 0.56 ± 0.06 18 1.00 TYP 0. TOP VIEW 19.00 SQUARE +0.70 17.70 –0.05 SQUARE 30° APPROX 0.50 R MAX ALL SIDES ALL EDGES +0.07 0.63 DIA –0.13 BOTTOM VIEW Hardware Design Guide, Revision 1 November 2, 2005 1 ...
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... Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc. Copyright © 2005 Agere Systems Inc. All Rights Reserved November 2, 2005 DS02-122SWCH-1 (Replaces DS02-122SWCH) Ball Count 240 6-6. 6- Time-Slot Interchanger Package Comcode PBGAM1 700046829 700078759* and V IHmin TSI-8 max. IL ...