ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 11

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

The Status Register – SREG
1187D–12/01
Table 2. ATtiny15L I/O Space
Note:
All ATtiny15L I/O and peripheral registers are placed in the I/O space. The I/O locations
are accessed by the IN and OUT instructions transferring data between the 32 general
purpose working registers and the I/O space. I/O registers within the address range $00
- $1F are directly bit-accessible using the SBI and CBI instructions. In these registers,
the value of single bits can be checked by using the SBIS and SBIC instructions. Refer
to the instruction set chapter for more details. For compatibility with future devices,
reserved bits should be written zero if accessed. Reserved I/O memory addresses
should never be written.
The I/O and peripheral control registers are explained in the following sections.
The AVR status register – SREG – at I/O space location $3F is defined as:
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in the interrupt mask registers –
GIMSK and TIMSK. If the global interrupt enable register is cleared (zero), none of the
interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared
by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s comple-
ment overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the
Instruction Set description for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic
operations. See the Instruction Set description for detailed information.
Bit
$3F
Read/Write
Initial Value
Address Hex
$06
$05
$04
1. Reserved and unused locations are not shown in the table.
R/W
7
0
I
Name
ADCSR
ADCH
ADCL
R/W
6
T
0
(1)
R/W
H
5
0
Function
ADC Control and Status Register
ADC Data Register High
ADC Data Register Low
(Continued)
R/W
S
4
0
R/W
V
3
0
R/W
N
2
0
R/W
1
Z
0
ATtiny15L
R/W
0
C
0
SREG
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