ATTINY15 ATMEL [ATMEL Corporation], ATTINY15 Datasheet - Page 36

• Manufacturer Part Number: ATTINY15
• Manufacturer: ATMEL [ATMEL Corporation]

EEPROM Read/Write
Access
The EEPROM Address
Register – EEAR
The EEPROM Data Register –
EEDR
The EEPROM Control Register
– EECR
36
ATtiny15L
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 4.6 - 8.2 ms, depending on the frequency of the
calibrated RC oscillator. See Table 16 for details. A self-timing function however, lets the
user software detect when the next byte can be written. If the user code contains code
that writes the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
some period of time to run at a voltage lower than specified as minimum for the clock
frequency used. CPU operation under these conditions is likely to cause the program
counter to perform unintentional jumps and eventually execute the EEPROM write code.
To secure EEPROM integrity, the user is advised to use an external under-voltage reset
circuit in this case.
In order to prevent unintentional EEPROM writes, a two-state write procedure must be
followed. Refer to the description of the EEPROM Control Register for details of this.
When the EEPROM is read or written, the CPU is halted for two clock cycles before the
next instruction is executed.
• Bit 7, 6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and will always read as zero.
• Bit 5..0 – EEAR5..0: EEPROM Address
The EEPROM Address Register (EEAR) specifies the EEPROM address in the 64 bytes
EEPROM space. The EEPROM data bytes are addresses linearly between 0 and 63.
The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
• Bit 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read opera-
tion, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
• Bit 7..4 – RES: Reserved Bits
These bits are reserved bits in the ATtiny15L and will always read as zero.
Bit
$1E
Read/Write
Initial vAlue
Bit
$1D
Read/Write
Initial Value
Bit
$1C
Read/Write
Initial value
CC
is likely to rise or fall slowly on Power-up/down. This causes the device for
MSB
R/W
R
R
7
–
0
7
0
7
–
0
R/W
R
R
6
–
0
6
0
6
–
0
EEAR5
R/W
R/W
R
X
5
–
0
5
5
0
EEAR4
R/W
R/W
R
X
4
–
0
4
4
0
EEAR3
EERIE
R/W
R/W
R/W
X
3
0
3
3
0
EEAR2
EEM-
R/W
R/W
R/W
WE
2
X
2
0
2
0
EEAR1
EEWE
R/W
R/W
R/W
X
1
X
1
1
0
EEAR0
EERE
R/W
R/W
LSB
R/W
X
0
0
0
0
0
1187D–12/01
EECR
EEAR
EEDR