T89C5115_08 ATMEL [ATMEL Corporation], T89C5115_08 Datasheet - Page 18

• Manufacturer Part Number: T89C5115_08
• Description: Low Pin Count 8-bit Microcontroller with A/D Converter and 16 KBytes Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Power Management
Reset Pin
At Power-up (cold reset)
18
AT89C5115
Two power reduction modes are implemented in the T89C5115: the Idle mode and the
Power-down mode. These modes are detailed in the following sections. In addition to
these power reduction modes, the clocks of the core and peripherals can be dynamically
divided by 2 using the X2 Mode detailed in Section “Clock”.
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a
high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of
the internal registers like SFRs, PC, etc. and to unpredictable behavior of the microcon-
troller. A warm reset can be applied either directly on the RST pin or indirectly by an
internal reset source such as a watchdog, PCA, timer, etc.
Two conditions are required before enabling a CPU start-up:
•
•
If one of these two conditions are not met, the microcontroller does not start correctly
and can execute an instruction fetch from anywhere in the program space. An active
level applied on the RST pin must be maintained until both of the above conditions are
met. A reset is active when the level VIH1 is reached and when the pulse width covers
the period of time where VDD and the oscillator are not stabilized. Two parameters have
to be taken into account to determine the reset pulse width:
•
•
To determine the capacitor the highest value of these two parameters has to be chosen.
The reset circuitry is shown in Figure 5.
Figure 5. Reset Circuitry
Table 12 and Table 13 give some typical examples for three values of VDD rise times,
two values of oscillator start-up time and two pull-down resistor values.
Table 12. Minimum Reset Capacitor for a 50K Pull-down Resistor
VDD must reach the specified VDD range,
The level on xtal1 input must be outside the specification (VIH, VIL).
VDD rise time (vddrst),
Oscillator startup time (oscrst).
oscrst/vddrst
20ms
5ms
VDD
Crst
820nF
2.7µF
1ms
RST pin
Rrst
Reset input circuitry
1.2µF
3.9µF
10ms
Internal reset
0
100ms
12µF
12µF
4128G–8051–02/08