ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 212

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

22.3.4
22.3.5
2545T–AVR–05/11
Data packet format
Combining address and data packets into a transmission
Figure 22-4. Address packet format.
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 22-5. Data packet format.
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 22-6 on page 213
transmitted between the SLA+R/W and the STOP condition, depending on the software protocol
implemented by the application software.
Transmitter
Aggregate
SDA from
SDA from
SCL from
Receiver
SDA
Master
SCL
SDA
SLA+R/W
START
Data MSB
shows a typical data transmission. Note that several data bytes can be
Addr MSB
1
1
2
2
Data byte
7
Addr LSB
Data LSB
8
7
ATmega48/88/168
ACK
9
R/W
8
ACK
STOP, REPEATED
9
START or next
data byte
212