ATMEGA48V_11 ATMEL [ATMEL Corporation], ATMEGA48V_11 Datasheet - Page 222

• Manufacturer Part Number: ATMEGA48V_11
• Description: 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

22.7
22.7.1
2545T–AVR–05/11
Transmission modes
Master transmitter mode
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be used in the same application. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system, some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described
along with figures detailing data transmission in each of the modes. These figures contain the
following abbreviations:
In
TWINT Flag is set. The numbers in the circles show the status code held in TWSR, with the
prescaler bits masked to zero. At these points, actions must be taken by the application to con-
tinue or complete the TWI transfer. The TWI transfer is suspended until the TWINT Flag is
cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate soft-
ware action. For each status code, the required software action and details of the following serial
transfer are given in
bits are masked to zero in these tables.
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver
(see
transmitted. The format of the following address packet determines whether Master Transmitter
or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if
SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.
Figure 22-12 on page 225
S:
Rs:
R:
W:
A:
A:
Data: 8-bit data byte
P:
SLA: Slave Address
Figure 22-11 on page
START condition
REPEATED START condition
Read bit (high level at SDA)
Write bit (low level at SDA)
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level at SDA)
STOP condition
Table 22-2 on page 224
223). In order to enter a Master mode, a START condition must be
to
Figure 22-18 on page
to
Table 22-5 on page
234, circles are used to indicate that the
ATmega48/88/168
233. Note that the prescaler
222