P89LPC913 PHILIPS [NXP Semiconductors], P89LPC913 Datasheet - Page 46

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P89LPC913

Manufacturer Part Number
P89LPC913
Description
8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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Product data
9.25.1 Software reset
9.25.2 Dual data pointers
9.26.1 General description
9.26.2 Features
9.26.3 Flash organization
9.25 Additional features
9.26 Flash program memory
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.
The P89LPC912/913/914 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be erased, read, and written as bytes. The Sector and
Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The
Chip Erase operation will erase the entire program memory. In-Circuit Programming
using standard commercial programmers is available. In addition, In-Application
Programming (IAP) and byte erase allows code memory to be used for non-volatile
data storage. On-chip erase and write timing generation contribute to a user-friendly
programming interface. The P89LPC912/913/914 Flash reliably stores memory
contents even after 100,000 erase and program cycles. The cell is designed to
optimize the erase and programming mechanisms. The P89LPC912/913/914 uses
V
The P89LPC912/913/914 program memory consists of four 256 byte sectors. Each
sector can be further divided into 16-byte pages. In addition to sector erase, page
erase, and byte erase, a 16-byte page register is included which allows from
1 to 16 bytes of a given page to be programmed at the same time, substantially
reducing overall programming time. In addition, erasing and reprogramming of
user-programmable configuration bytes including UCFG1, the Boot Status Bit, and
the Boot Vector is supported.
DD
Programming and erase over the full operating voltage range.
Byte-erase allowing code memory to be used for data storage.
Read/Programming/Erase using ICP.
Any flash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the Flash for each sector.
More than 100,000 minimum erase/program cycles for each byte.
10-year minimum data retention.
as the supply voltage to perform the Program/Erase algorithms.
Rev. 03 — 17 December 2004
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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