P89LPC915FDH NXP [NXP Semiconductors], P89LPC915FDH Datasheet - Page 27

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P89LPC915FDH

Manufacturer Part Number
P89LPC915FDH
Description
8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter
Manufacturer
NXP [NXP Semiconductors]
Datasheets

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Table 9:
* indicates SFRs that are bit addressable.
[1]
[2]
[3]
[4]
[5]
[6]
Name
TAMOD
TCON*
TH0
TH1
TL0
TL1
TMOD
TRIM
WDCON
WDL
WFEED1
WFEED2
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC915/916/917 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
After reset, the value is 111001x1, i.e., PRE[2:0] are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset. Other
resets will not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
P89LPC917 Special function registers
Description
Timer 0 and 1 auxiliary mode
Timer 0 and 1 control
Timer 0 HIGH
Timer 1 HIGH
Timer 0 LOW
Timer 1 LOW
Timer 0 and 1 mode
Internal oscillator trim register
Watchdog control register
Watchdog load
Watchdog feed 1
Watchdog feed 2
Bit address
SFR
addr.
8CH
8DH
8AH
8BH
A7H
C1H
C2H
C3H
8FH
88H
89H
96H
Bit functions and addresses
…continued
T1GATE
RCCLK
PRE2
MSB
TF1
8F
-
ENCLK
T1C/T
PRE1
TR1
8E
-
TRIM.5
PRE0
T1M1
TF0
8D
-
TRIM.4
T1M2
T1M0
TR0
8C
-
T0GATE
TRIM.3
IE1
8B
-
-
WDRUN
TRIM.2
T0C/T
IT1
8A
-
WDTOF
TRIM.1
T0M1
IE0
89
-
WDCLK
TRIM.0
T0M2
T0M0
LSB
IT0
88
Reset value
Hex
00
00
00
00
00
00
00
FF
[5] [6]
[4] [6]
Binary
xxx0xxx0
00000000
00000000
00000000
00000000
00000000
00000000
11111111

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