P89LPC920FDH PHILIPS [NXP Semiconductors], P89LPC920FDH Datasheet - Page 18

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P89LPC920FDH

Manufacturer Part Number
P89LPC920FDH
Description
8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM
Manufacturer
PHILIPS [NXP Semiconductors]

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P89LPC920FDH
Manufacturer:
FSC
Quantity:
5
Philips Semiconductors
Table 6:
9397 750 12285
Product data
Clock source
On-chip oscillator or watchdog oscillator
External clock input
Low/medium/high speed oscillator
(external crystal or resonator)
Fig 6. Interrupt sources, interrupt enables, and power-down wake-up sources.
(RTCCON.1)
WDOVF
Number of I/O pins available
RTCF
ERTC
8.12.1 Port configurations
8.12 I/O ports
The P89LPC920/921/922 has three I/O ports: Port 0, Port 1, and Port 3. Ports 0 and
1 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available
depend upon the clock and reset options chosen, as shown in
All but three I/O port pins on the P89LPC920/921/922 may be configured by software
to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard
80C51 port outputs), push-pull, open drain, and input-only. Two configuration
registers for each port select the output type for each port pin.
P1.5 (RST) can only be an input and cannot be configured.
P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
EA (IE0.7)
TI & RI/RI
ES/ESR
EWDRT
BOPD
CMF2
CMF1
EI2C
EBO
EKBI
KBIF
EST
EX0
EX1
ET0
ET1
TF0
TF1
IE0
IE1
EC
TI
SI
Reset option
No external reset (except during power-up)
External RST pin supported
No external reset (except during power-up)
External RST pin supported
No external reset (except during power-up)
External RST pin supported
Rev. 06 — 21 November 2003
8-bit microcontrollers with two-clock 80C51 core
P89LPC920/921/922
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
002aaa418
Number of I/O pins
(20-pin package)
18
17
17
16
16
15
INTERRUPT
TO CPU
WAKE-UP
(IF IN POWER-DOWN)
Table
6.
18 of 45

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