LPC2109FBD64/01 NXP [NXP Semiconductors], LPC2109FBD64/01 Datasheet - Page 18

• Manufacturer Part Number: LPC2109FBD64/01
• Description: Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Product data sheet
LPC2109_2119_2129_6
6.14.1 Features
6.14.2 Features available in LPC2109/2119/2129/01 only
6.15.1 Features
6.15 Watchdog timer
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
The LPC2109/2119/2129/01 can count external events on one of the capture inputs if the
external pulse lasts at least one half of the period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs, or used as external
interrupts.
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
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A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Timer or external event counter operation
Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs per timer corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Timer can count cycles of either the peripheral clock (PCLK) or an externally supplied
clock.
When counting cycles of an externally supplied clock, only one of the timer’s capture
inputs can be selected as the timer’s clock. The rate of such a clock is limited to
PCLK / 4. Duration of HIGH/LOW levels on the selected CAP input cannot be shorter
than 1 / (2PCLK).
Internally resets chip if not periodically reloaded.
Debug mode.
Rev. 06 — 10 December 2007
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
© NXP B.V. 2007. All rights reserved.
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