LPC2460FET208 PHILIPS [NXP Semiconductors], LPC2460FET208 Datasheet - Page 22

• Manufacturer Part Number: LPC2460FET208
• Description: Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
Table 4.
LPC2460_0
Preliminary data sheet
Symbol
P4[29]/BLS3/
MAT2[1]/RXD3
P4[30]/CS0
P4[31]/CS1
ALARM
USB_D−2
DBGEN
TDO
TDI
TMS
TRST
TCK
RTCK
RSTOUT
RESET
XTAL1
XTAL2
RTCX1
RTCX2
V
V
V
SSIO
SSCORE
SSA
Pin description
Pin
176
187
193
37
52
9
2
4
6
8
10
206
29
35
44
46
34
36
33, 63,
77, 93,
114,
133,
148,
169,
189,
200
32, 84,
172
22
[1]
[1]
[1]
[1]
[1]
[8]
[1]
[7]
[8]
[8]
[8]
[8]
[10]
[1]
[1]
[1]
[1]
[9]
[9]
…continued
Ball
B10
B7
A4
N1
U1
F4
D3
C2
E3
D1
E2
C3
K3
M2
M4
N4
K2
L2
L3, T5,
R9,
P12,
N16,
H14,
E15,
A12,
B6, A2
K4, P10,
D12
J2
[10]
[8]
[1]
[1]
[1]
[1]
[1]
[8]
[8]
[1]
[1]
[1]
[1]
[8]
[7]
[8]
[1]
[9]
[9]
Type
I/O
O
O
I
I/O
O
I/O
O
O
I/O
I
O
I
I
I
I
I/O
O
I
I
O
I
O
I
I
I
Rev. 00.01 — 5 October 2007
Description
P4[29] — General purpose digital input/output pin.
BLS3 — LOW active Byte Lane select signal 3.
MAT2[1] — Match output for Timer 2, channel 1.
RXD3 — Receiver input for UART3.
P4[30] — General purpose digital input/output pin.
CS0 — LOW active Chip Select 0 signal.
P4[31] — General purpose digital input/output pin.
CS1 — LOW active Chip Select 1 signal.
ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when
a RTC alarm is generated.
USB_D−2 — USB port 2 bidirectional D− line.
DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO — Test Data out for JTAG interface.
TDI — Test Data in for JTAG interface.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
TCK — Test Clock for JTAG interface. This clock must be slower than
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0])
to operate as Trace port after reset.
RSTOUT — This is a 1.8 V pin. LOW on this pin indicates LPC2460 being
in Reset state.
external reset input: A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground: 0 V reference for the digital I/O pins.
ground: 0 V reference for the core.
analog ground: 0 V reference. This should nominally be the same
voltage as V
SS
, but should be isolated to minimize noise and error.
Fast communication chip
LPC2460
© NXP B.V. 2007. All rights reserved.
22 of 67
1
⁄
6