LPC2880FET180 PHILIPS [NXP Semiconductors], LPC2880FET180 Datasheet - Page 21

• Manufacturer Part Number: LPC2880FET180
• Description: 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
LPC2880_LPC2888_1
Preliminary data sheet
6.16.1 Features
6.16 Analog I/O
6.17 USB 2.0 high-speed device controller
The analog I/O system includes an I
converter, and a dual D/A converter. Each channel includes a separate 4 sample FIFO.
Each of the two ADC inputs includes a Programmable Gain Amplifier (PGA). A separate
input, which can be routed to either ADC, also include an additional Low Noise Amplifier
(LNA).
Each DAC has associated pins for unbuffered and amplified outputs.
The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The host schedules transactions in 1 ms frames. Each frame contains an SoF marker and
transactions that transfer data to/from device endpoints. Each device can have a
maximum of 16 logical or 32 physical endpoints. There are 4 types of transfers defined for
the endpoints. Control transfers are used to configure the device. Interrupt transfers are
used for periodic data transfer. Bulk transfers are used when rate of transfer is not critical.
Isochronous transfers have guaranteed delivery time but no error correction.
The LPC2880/LPC2888 USB controller enables 480 Mbit/s or 12 Mbit/s data exchange
with a USB host controller. It includes a USB controller, a DMA engine, and a USB 2.0
ATX physical interface.
The USB controller consists of the protocol engine and buffer management blocks. It
includes an SRAM that is accessible to the DMA engine and to the processor via the
register interface.
The DMA engine is an AHB master, having direct access to all ARM memory space but
particularly to on-chip RAM. Each USB endpoint that requires its data to be transferred via
DMA is allocated to a logical DMA channel in the DMA engine.
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Power-down mode.
Measurement range 0 V to 3.3 V.
10-bit conversion time
Single or continuous conversion mode.
I
I
Dual 16-bit A/D converters with individual inputs routed through programmable gain
amplifiers. Each ADC can alternatively take its input from a single pin that includes an
additional low noise amplifier. Input takes place through a 4 sample FIFO.
Dual 16-bit D/A converters. Each DAC includes both a direct output and an amplified
output. Output takes place through a 4 sample FIFO.
2
2
S-bus input channel with a 4 sample FIFO for stereo Digital Analog Input (DAI).
S-bus output channel with a 4 sample FIFO for stereo Digital Analog Output (DAO).
16/32-bit ARM microcontrollers with external memory interface
Rev. 01 — 22 June 2006
2.44 s.
2
S input channel, an I
LPC2880; LPC2888
2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
S output channel, a dual A/D
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