ST7FMC1K2TC STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2TC Datasheet - Page 156
ST7FMC1K2TC
Manufacturer Part Number
ST7FMC1K2TC
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST7FMC1K2TC.pdf
(308 pages)
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ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont’d)
10.6.6.7 Protection for Z
To avoid an erroneous detection of a hardware
zero-crossing event, a filter can be enabled by set-
ting the PZ bit in the MCRA register. This filter will
ensure the detection of a Z
transition between D event and Z
Without this protection, Z
directly on the current sample in comparison with
the expected state at the output of the phase com-
parator. For example, if a falling edge transition
(meaning a transition from 1 to 0 at the output of
the phase comparator) is configured for Z
through the CPB bit in MCRB register, then, the
state 0 is expected at the comparator output and
Figure 83. Protection of Z
156/308
1
Phase
Comparator
+
-
V
I
Fz
C
Sampling clock
H
H
Instantaneous
edge
event detection is done
Current sample
H
D
CP
event detection
H
C Rz
event detection
S
R
event on an edge
Q
Q
H
event.
D
CP
H
event
S
R
D
CP
Previous sample
Q
Q
S
R
Q
Q
once this state is detected, the Z
ated without any verification that the state at the
comparator output of the previous sample was 1.
The purpose of this protection filter is to be sure
that the state of the comparator output at the sam-
ple before was really the opposite of the current
state which is generating the Z
filter, the Z
transition level comparison.
This filter is not needed in sensor mode (SR=1)
and for simulated zero-crossing event (Z
ation.
When the PZ bit is set, the Z event filter ZEF[3:0] in
the MZFR register is ignored.
Rz
Fz
H
event generation is done on edge
Falling/Rising Edge
MCRB register MPOL register
V Voltage mode
I Current mode
Rz Rising edge zero-crossing
Fz Falling edge zero-crossing
C Commutation event
CPB* bit
Direct/Filter PZ
MCRA register
bit 1
H
H
F
D
event. With this
event is gener-
ZVD bit
S
) gener-
Z
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