ST7FMC1K2TC STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2TC Datasheet - Page 51

• Manufacturer Part Number: ST7FMC1K2TC
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see
6.4 on page 36
register).
The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see Table 8, “Interrupt Mapping,” on
page 43) or a RESET. When exiting ACTIVE-
HALT mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
MCCSR
OIE bit
0
1
HALT mode
ACTIVE-HALT mode
Power Saving Mode entered when HALT
for more details on the MCCSR
instruction is executed
Figure
section
29).
Figure 28. ACTIVE-HALT Timing Overview
Figure 29. ACTIVE-HALT Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 8, “Interrupt Mapping,” on page 43 for more
details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
[MCCSR.OIE=1]
INSTRUCTION
HALT INSTRUCTION
RUN
N
(MCCSR.OIE=1)
HALT
INTERRUPT
ACTIVE
HALT
Y
256 OR 4096 CPU
CYCLE DELAY
INTERRUPT
3)
RESET
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
CPU
I[1:0] BITS
CPU
I[1:0] BITS
N
CYCLE DELAY
ST7MC1/ST7MC2
RESET
Y
1)
VECTOR
FETCH
RUN
2)
XX
XX
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
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4)
4)
1