MC9S08QD2MPS FREESCALE [Freescale Semiconductor, Inc], MC9S08QD2MPS Datasheet - Page 62

• Manufacturer Part Number: MC9S08QD2MPS
• Description: 8-Bit HCS08 Central Processor Unit (CPU)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
Chapter 5 Resets, Interrupts, and General System Control
5.8.3
This high-page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
62
BDFR is writable only through serial background debug commands, not from user programs.
Reset:
BDFR
Field
Field
ILOP
ILAD
COP
LVD
5
4
3
1
0
W
R
System Background Debug Force Reset Register (SBDFR)
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address
1 Reset caused by an illegal address
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program. To enter user mode, PTA4/TPM2CH0O/BKGD/MS must be high immediately
after issuing WRITE_BYTE command. To enter BDM, PTA4/TPM2CH0O/BKGD/MS must be low immediately
after issuing WRITE_BYTE command. See
0
0
7
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
Table 5-4. SRS Register Field Descriptions (continued)
0
0
6
Table 5-5. SBDFR Register Field Descriptions
MC9S08QD4 Series MCU Data Sheet, Rev. 3
0
0
5
A.8.1, “Control
0
0
4
Description
Description
Timing,” for more information.
3
0
0
0
0
2
Freescale Semiconductor
0
0
1
BDFR
0
0
0
1