MC9S08QE128 FREESCALE [Freescale Semiconductor, Inc], MC9S08QE128 Datasheet - Page 14

• Manufacturer Part Number: MC9S08QE128
• Description: 8-Bit HCS08 Central Processor Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Electrical Characteristics
For most applications, P
is:
Solving
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P
for a known T
for any value of T
3.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
14
Equation 1
ESD Protection and Latch-Up Immunity
1
A
. Using this value of K, the values of P
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
A
No.
.
Machine
Latch-up
1
2
3
4
and
Human
Model
Body
I/O
Equation 2
<< P
Human body model (HBM)
Machine model (MM)
Charge device model (CDM)
Latch-up current at T
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Series resistance
Storage capacitance
Number of pulses per pin
Series resistance
Storage capacitance
Number of pulses per pin
Minimum input voltage limit
Maximum input voltage limit
Table 7. ESD and Latch-Up Protection Characteristics
int
and can be neglected. An approximate relationship between P
for K gives:
Table 6. ESD and Latch-up Test Conditions
K = P
Rating
Description
D
P
× (T
1
A
D
= 85°C
= K ÷ (T
A
D
+ 273°C) + θ
and T
J
J
+ 273°C)
can be obtained by solving
Symbol
V
V
V
I
JA
HBM
CDM
LAT
MM
Symbol
R1
R1
× (P
—
—
C
C
D
)
2
± 2000
± 200
± 500
± 100
Min
Value
1500
– 2.5
100
200
7.5
Equation 1
3
0
3
Max
—
—
—
—
D
and T
and
Freescale Semiconductor
Unit
pF
pF
Ω
Ω
J
V
V
Equation 2
(if P
Unit
mA
V
V
V
D
I/O
(at equilibrium)
is neglected)
iteratively
Eqn. 2
Eqn. 3