COP8-PGMA-DS NSC [National Semiconductor], COP8-PGMA-DS Datasheet - Page 32

• Manufacturer Part Number: COP8-PGMA-DS
• Description: 8-Bit One-Time Programmable (OTP) Microcontroller with UART and Three Multi-Function Timers
• Manufacturer: NSC [National Semiconductor]

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Instruction Set
INSTRUCTION SET
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ADD
ADC
SUBC
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
X
X
LD
LD
LD
LD
LD
X
X
LD
LD
LD
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
VIS
JMPL
JMP
JP
JSRL
JSR
JID
RET
RETSK
RETI
INTR
NOP
A Meml
A Meml
A Meml
A Meml
A Imm
A Meml
A Meml
MD Imm
A Meml
A Meml
A Meml
Reg
A Mem
A X
A Meml
A X
B Imm
Mem Imm
Reg Imm
A B
A X
A B
A X
A
A
A
A
A
A
A
A
A
Addr
Addr
Disp
Addr
Addr
B
Mem
Mem
Mem
g
g
g
g
g
Imm
(Continued)
ADD
ADD with Carry
Subtract with Carry
Logical AND
Logical AND Immed Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg Skip if Zero
Set BIT
Reset BIT
IF BIT
Reset PeNDing Flag
EXchange A with Memory
EXchange A with Memory X
LoaD A with Memory
LoaD A with Memory X
LoaD B with Immed
LoaD Memory Immed
LoaD Register Memory Immed
EXchange A with Memory B
EXchange A with Memory X
LoaD A with Memory B
LoaD A with Memory X
LoaD Memory B Immed
CLeaR A
INCrement A
DECrement A
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
Reset C
IF C
IF Not C
POP the stack into A
PUSH A onto the stack
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
Jump SubRoutine Long
Jump SubRoutine
Jump InDirect
RETurn from subroutine
RETurn and SKip
RETurn from Interrupt
Generate an Interrupt
No OPeration
32
A
A
HC
A
HC
A
Skip next if (A and Imm)
A
A
Compare MD and Imm Do next if MD
Compare A and Meml Do next if A
Compare A and Meml Do next if A
Compare A and Meml Do next if A
Do next if lower 4 bits of B
Reg
1 to bit Mem (bit
0 to bit Mem
If bit in A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A
A
A
A
B
Mem
Reg
A
A
A
A
A
A
A
A
A
C
C
A7
C
C
IF C is true do next instruction
If C is not true do next instruction
SP
PU
PC
PC9
PC
PL
SP
SP
skip next instruction
SP
PC
B
SP
SP
SP
SP
a
a
a
A
A
A
A and Meml
A or Meml
A xor Meml
Meml
Imm
0
A
A
ROM (PU A)
BCD correction of A (follows ADC SUBC)
A7
A7
1 HC
0 HC
2 PL
2 PL
2 PL
X
B (B
X (X
A4
ROM (PU A)
SP
ii (ii
PC
PC
Mem
Half Carry
Half Carry
Imm (B
b
b
a
a
a
0
X
B (B
X (X
VU PL
Reg
Imm
A SP
PL SP
PL SP
PL SP
Imm
MemI
1
a
Meml
Meml
1
a
a
e
b
1 A
r (r is
1
15 bits 0 to 32k)
i (i
A3
1
0
1 Skip if Reg
b
b
b
X
e
SP PU
SP PU
B
a
a
e
SP PU
X
g
B
SP
1
1
1
g
b
12 bits)
B
C C
C C
0 to 7 immediate)
g
1)
g
1)
g
VL
A0
A0
31 to
A0
1)
b
1)
SP
1)
e
1
PU SP
PU SP
PU SP
i
0
a
Carry
Carry
C
C
Imm
SP
32 except 1)
e
SP
SP
b
b
b
b
0
b
b
2 PC
2 PC9
1
2 PC
l
1
1 GIE
e
i
Meml
Meml
e
Meml
Imm
ii
0FF
0
1
i