M30245_06 RENESAS [Renesas Technology Corp], M30245_06 Datasheet - Page 115

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M30245_06

Manufacturer Part Number
M30245_06
Description
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Operation
Note
2.5.5 Operation of Serial Interface Special Function (reception in slave mode with
In receiving data in serial interface special function slave mode, choose functions from those listed in
Table 2.5.4. Operations of the circled items are described below. Figure 2.5.17 shows the operation
timing, and Figures 2.5.18 and 2.5.19 show the set-up procedures.
clock delay)
Table 2.5.4. Choosed functions
(1) An SSi port is input "L" level which outputs from the transmitter side IC port.
(2) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
(3) In synchronization with the first rising edge of the transfer clock, the input signal to the SRxDi
(4) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
(5) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
• Set CLKi and SRxDi pins' port direction register to “0”.
Transfer clock
source
CLK polarity
Continuous receive
mode
and the transmit enable bit to “1”, makes the data receivable status ready.
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
register is transmitted to the UARTi receive buffer register. At this time, the receive complete
flag and the UARTi receive interrupt request bit goes to “1”.
is read.
____
Item
Item
page 106 of 354
O
O
O
Disabled
Output reception data at
the falling edge of the
transfer clock
Enabled
Internal clock (f
External clock (CLKi pin)
Output reception data at
the rising edge of the
transfer clock
Set-up
1
/ f
8
/ f
32
)
SSi port function
enable
Clock phase set
Serial input port set
Item
2. Serial Interface Special Function
O
O
O
SSi function disabled
SSi function enabled
With clock delay
Without clock delay
T
(master mode)
ST
(slave mode)
X
Di, R
X
Di, SR
X
Set-up
Di selected
X
Di selected

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