M30245_06 RENESAS [Renesas Technology Corp], M30245_06 Datasheet - Page 94

• Manufacturer Part Number: M30245_06
• Description: RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
2.5 Serial Interface Special Function
2.5.1 Overview
Serial interface special function can control communications on the serial bus using SSi input pins. The
following is an overview of the serial interface special function.
(1) Transmission/reception format
(2) Transfer rate
(3) Error detection
(4) How to deal with an error
(5) Function selection
8-bit data
If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit
rate generator division, becomes the transfer rate. The bit rate generator count source can be se-
lected from the following: f
clock by 1, 8, and 32 respectively.
Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK
pin becomes the transfer rate.
Fault error can be detected in the master mode.
When an “L” signal is input to an SSi pin in the multiple master system, it is judged there is another
master existed, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the fault
error interrupt request bit becomes "1" and a fault error interrupt is generated.
When the fault error flag is set to “0”, output is restored to the clock output and data output pins. In the
master mode, if an SSi input pin is H level, “0” can be written for the fault error flag. When an SSi input
pin is L level, “0” cannot be written for the fault error flag. In the slave mode, the “0” can be written for
the fault error flag regardless of the input to the SSi input pins.
For serial interface special function, the following functions can be selected:
(a) Function for choosing CLK polarity
(b) Function for setting clock phase
(c) Function for setting serial input pin
This function switches the CLK polarity of the transfer clock. The following operations are available:
• Data is input at the falling edge of the transfer clock, and is output at the rising edge.
• Data is input at the rising edge of the transfer clock, and is output at the falling edge.
This function switches the phase of the transfer clock. Choose either of the following:
•Without clock delay
•With clock delay
This function switches the serial bus control privilege between the master mode and slave mode.
Choose either of the following:
• Master mode
• Slave mode
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_____
1
, f
8
, and f
_____
32
. Clocks f
_____
1
, f
8
, and f
32
are derived by dividing the CPU’s main
2. Serial Interface Special Function
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