LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 207
LM3S101-IRN20
Manufacturer Part Number
LM3S101-IRN20
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-IRN20.pdf
(300 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S101-IRN20C0X
Manufacturer:
LUMINARYM
Quantity:
20 000
- Current page: 207 of 300
- Download datasheet (2Mb)
October 5, 2006
Reset
Reset
Type
Type
Bit/Field
31:10
UART Control (UARTCR)
Offset 0x030
6:1
9
8
7
0
RO
RO
31
15
0
0
Register 7: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are
written. If the UART is disabled during a transmit or receive operation, the current transaction is
completed prior to the UART stopping.
RO
RO
30
14
0
0
UARTEN
reserved
reserved
Name
RXE
TXE
LBE
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0
1
1
0
0
0
RXE
R/W
RO
25
0
9
1
Preliminary
Reserved bits return an indeterminate value, and should never
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled.
When the UART is disabled in the middle of a receive, it
completes the current character before stopping.
UART Transmit Enable
If this bit is set to 1, the transmit section of the UART is enabled.
When the UART is disabled in the middle of a transmission, it
completes the current character before stopping.
UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
be changed.
UART Enable
If this bit is set to 1, the UART is enabled. When the UART is
disabled in the middle of transmission or reception, it completes
the current character before stopping.
TXE
R/W
RO
24
0
8
1
reserved
LBE
R/W
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
reserved
RO
RO
19
0
3
0
LM3S101 Data Sheet
RO
RO
18
0
2
0
RO
RO
17
0
1
0
UARTEN
R/W
RO
16
0
0
0
207
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