LM3S101-IRN20 ETC2 [List of Unclassifed Manufacturers], LM3S101-IRN20 Datasheet - Page 75
LM3S101-IRN20
Manufacturer Part Number
LM3S101-IRN20
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S101-IRN20.pdf
(300 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM3S101-IRN20C0X
Manufacturer:
LUMINARYM
Quantity:
20 000
- Current page: 75 of 300
- Download datasheet (2Mb)
October 5, 2006
Reset
Reset
Type
Type
Bit/Field
31:16
15:14
13:5
XTAL to PLL Translation (PLLCFG)
Offset 0x064
4:0
RO
RO
31
15
0
-
OD
Register 18: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 71).
RO
RO
30
14
0
-
reserved
Name
OD
R
RO
RO
F
29
13
0
-
RO
RO
28
12
0
-
Type
RO
RO
27
11
RO
RO
RO
RO
0
-
RO
RO
26
10
0
-
Reset
RO
RO
25
F
0
9
-
0
Preliminary
-
-
-
RO
RO
24
0
8
-
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
This field specifies the value supplied to the PLL’s OD input.
This field specifies the value supplied to the PLL’s F input.
This field specifies the value supplied to the PLL’s R input.
RO
RO
23
0
7
-
RO
RO
22
0
6
-
RO
RO
21
0
5
-
RO
RO
20
0
4
-
RO
RO
19
0
3
-
LM3S101 Data Sheet
RO
RO
18
0
2
-
R
RO
RO
17
0
1
-
RO
RO
16
0
0
-
75
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