Z86D99 ZILOG [Zilog, Inc.], Z86D99 Datasheet - Page 30

• Manufacturer Part Number: Z86D99
• Description: Low-Voltage Micro controllers with ADC
• Manufacturer: ZILOG [Zilog, Inc.]

PS003807-1002
Note:
instruction pipeline by executing a NOP (Op Code =
appropriate sleep instruction. For example:
or
HALT
HALT mode suspends instruction execution and turns off the internal CPU clock
(SCLK). The on-chip oscillator circuit remains active, so the internal Timer clock
(TCLK) continues to run and is applied to the counter/timers and interrupt logic.
An interrupt request, either internally or externally generated, must be executed
(enabled) to exit HALT mode. After the interrupt service routine, the program con-
tinues from the instruction immediately following the HALT.
The HALT mode can also be exited by a POR. In this case, the program execution
restarts at the reset address 000Ch .
STOP
STOP mode provides the lowest possible device standby current. This instruction
turns off both the internal CPU clock (SCLK) and internal Timer clock (TCLK) and
reduces the standby current to the minimum.
The STOP mode is terminated by a POR or SMR source. Terminating the STOP
mode causes the processor to restart the application program at address
Stop Mode Recovery Sources
Exiting STOP mode using an SMR source is greatly simplified in the Z86D99/
Z86L99 family. The Z86D99/Z86L99 family of products allows 16 individual I/O
When the STOP instruction is executed, the microcontroller goes into the
STOP mode despite any state/change of the state of the port. The ports
need to be checked immediately before the NOP and STOP instructions to
ensure the right input logic before waiting for the change of the ports.
Mnemonic Comment
NOP
STOP
Mnemonic Comment
NOP
HALT
P
; clear the pipeline
; enter STOP mode
; clear the pipeline
; enter HALT mode
R
E
L
I
M
Z86D990/Z86D991 OTP and Z86L99X ROM
I
Low-Voltage Microcontrollers with ADC
N
Op Code
FFh
6Fh
Op Code
FFh
7Fh
A
R
Y
FFh
) immediately before the
000Ch
.
23