SC68C752BIB48 PHILIPS [NXP Semiconductors], SC68C752BIB48 Datasheet - Page 18

• Manufacturer Part Number: SC68C752BIB48
• Description: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola uP interface
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
SC68C752B_3
Product data sheet
6.8 Break and time-out conditions
6.9 Programmable baud rate generator
An RX idle condition is detected when the receiver line, RX, has been HIGH for
4 character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TX line is pulled LOW. A break condition is activated
by setting LCR[6].
The SC68C752B UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (2
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure
formula for the divisor is:
Where:
Remark: The default value of prescaler after reset is divide-by-1.
Figure 12
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the
least significant and most significant byte of the baud rate divisor. If DLL and DLH are both
zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the transmit
and receive clock rates.
Table 8
1.8432 MHz and 3.072 MHz, respectively.
Figure 13
divisor
Fig 12. Prescaler and baud rate generator block diagram
prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
XTAL1
XTAL2
12. The output frequency of the baud rate generator is 16
=
and
-------------------------------------------------------------------------------- -
shows the internal prescaler and baud rate generator circuitry.
shows the crystal clock circuit reference.
XTAL1 crystal input frequency
---------------------------------------------------------------------------
Table 9
OSCILLATOR
desired baud rate 16
INTERNAL
LOGIC
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
show the baud rate and divisor correlation for crystal with frequency
Rev. 03 — 29 November 2005
prescaler
input clock
(DIVIDE-BY-1)
(DIVIDE-BY-4)
PRESCALER
PRESCALER
LOGIC
LOGIC
MCR[7] = 0
MCR[7] = 1
reference
clock
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
16
GENERATOR
BAUD RATE
LOGIC
SC68C752B
1). An additional
the baud rate. The
002aaa233
internal
baud rate
clock for
transmitter
and receiver
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