SC68C752BIB48 PHILIPS [NXP Semiconductors], SC68C752BIB48 Datasheet - Page 9

• Manufacturer Part Number: SC68C752BIB48
• Description: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola uP interface
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
SC68C752B_3
Product data sheet
Fig 4. Auto flow control (Auto-RTS and Auto-CTS) example
Fig 5. RTS functional timing
D7 to D0
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in
RTS
R/W
RX
6.2.1 Auto-RTS
Start
Auto-RTS data flow control originates in the receiver block (see
SC68C752B” on page
levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below
the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached,
RTS is de-asserted. The sending device (for example, another UART) may send an
additional byte after the trigger level is reached (assuming the sending UART has another
byte to send) because it may not recognize the de-assertion of RTS until it has begun
sending the additional byte. RTS is automatically reasserted once the receiver FIFO
reaches the resume trigger level programmed via TCR[7:4]. This re-assertion allows the
sending device to resume transmission.
FIFO
FIFO
TX
RX
byte N
UART 1
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
Stop
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 03 — 29 November 2005
3).
RTS
CTS
Start
RX
TX
Figure 5
byte N
1
shows RTS functional timing. The receiver FIFO trigger
1
TX
CTS
RX
RTS
2
Stop
TO SERIAL
SERIAL TO
PARALLEL
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
UART 2
N
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Section
Figure 1 “Block diagram of
FIFO
FIFO
SC68C752B
RX
TX
N
1
6.2.1.
002aaa228
002aab086
Start
D7 to D0
9 of 49