PA7536J-15 ANACHIP [Anachip Corp], PA7536J-15 Datasheet - Page 4

• Manufacturer Part Number: PA7536J-15
• Description: PEEL Array-TM Programmable Electrically Erasable Logic Array
• Manufacturer: ANACHIP [Anachip Corp]

Input Cells (INC)
Input cells (INC) are included on dedicated input pins. The
block diagram of the INC is shown in Figure 6. Each INC
consists of a multiplexer and a register/transparent latch,
which can be clocked from various sources selected by the
global cell. The register is rising edge clocked. The latch is
transparent when the clock is high and latched on the
clock’s failing edge. The register/latch
bypassed for a non registered input.
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the
LCCs in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-
state buffer and an output polarity control. The register/
latch can be clocked from a variety of sources determined
by the global cell. It can also be bypassed for a non-
registered input. A feature of the 7536 IOC is the use of
SUM-D as a feed-back to the array when the I/O pin is a
dedicated output. This allows for additional buried registers
and logic paths. (See Figure 8 & Figure 9).
Figure 8. LCC & IOC With Two Outputs
Figure 9. LCC & IOC With Three Outputs
A
B
C
D
C
D
A
B
Buried register or
logic paths
Input w ith optional
register/latch
D Q
D Q
O E
1
2
3
1
2
Q D
Q D
I/O w ith
independent
output enable
08-16-009A
08-16-008A
O utput
I/O
can also be
4
Global Cells
The global cells, shown in Figure 10, are used to direct
global clock signals and/or control terms to the LCCs, IOCs
and INCs. The global cells allow a clock to be selected
from the CLK1 pin, CLK2 pin, or a product term from the
logic array (PCLK). They also provide polarity control for
IOC clocks enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has
its own polarity control. The global cell includes sum-of-
products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to
save product terms for loadable counters and state
machines (see Figure 11).
global cells that divide the LCC and IOCs into two groups,
A and B. Half of the LCCs and IOCs use global cell A, half
use global cell B. This means, for instance, two high-speed
global clocks can be used among the LCCs.
Figure 10. Global Cells
Figure 11. Register Type Change Feature
Reg-Type from G lobal Cell
Reg-Type
Preset
PCLK
PCLK
Reset
CLK2
CLK2
CLK1
CLK1
D
T
R
R
P
P
Q
Q
G lobal C ell: LC C & IO C
Global C ell: IN C
R e g is te r T yp e C h a n g e F e a tu re
G lobal Cell can dynam ically change user-
selected LCC registers from D to T or from D
to JK. This saves product terms for loadable
counters or sta te m achines. Use as D register
to load, use as T or JK to count. Tim ing allo ws
dynam ic opera tion.
E x a m p le :
Product terms for 10 bit loadable binary co unter
D uses 57 prod uct term s (47 count, 10 load )
T uses 30 prod uct term s (10 count, 20 load )
D/T uses 20 product term s (10 count, 10 lo ad)
M UX
M UX
M UX
The PA7536 provides two
08-16-010A
LCC Resets
INC Clocks
LCC Clocks
IO C Clocks
LCC Reg-Typ e
G roup A & B
LCC Presets
08-16-011A
04-02-052A