PA7536J-15 ANACHIP [Anachip Corp], PA7536J-15 Datasheet - Page 9

• Manufacturer Part Number: PA7536J-15
• Description: PEEL Array-TM Programmable Electrically Erasable Logic Array
• Manufacturer: ANACHIP [Anachip Corp]

Figure 16. Sequential Timing – Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V
2.Test points for Clock and V
3. I/O pins are 0V or V
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
7. t
8. “System-clock” refers to pin 1 or pin 28 high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
12. Test loads are specified in Section 5 of the Data Book.
13. “Async. Clock” refers to the clock from the Sum term (OR gate).
for periods less than 20ns.
10% and 90% levels.
10% and 90% points, timing reference levels of 1.5V (unless
otherwise specified).
end of Section 6 for V
to V
OE
programmed as a 10-bit D-type counter.
is measured from input transition to V
OH
-0.1V or V
OL
CC
+0.1V.
REF
.
value). t
CC
in t
R
,t
OD
F
,t
CL
is measured from input transition
,t
CH
REF
, and t
±0.1V (See test loads at
RESET
are referenced at
9
14. The “LCC” term indicates that the timing parameter is applied to the
15. This refers to the Sum-D gate routed to the IOC register for an
16. The term “input” without any reference to another term refers to an
17. The parameter t
18. Typical (typ) ICC is measured at T
LCC register. The “IOC” term indicates that the timing parameter is
applied to the IOC register. The “LCC/IOC” term indicates that the
timing parameter is applied to both the LCC and IOC registers. The
“LCC/IOC/INC” term indicates that the timing parameter is applied to
the LCC,IOC, and INC registers.
additional buried register.
(external) input pin.
is always slower than the data from the pin or input by the absolute
value of (t
from the pin or input is required, i.e. the external data and clock can
be sent to the device simultaneously. Additionally, the data from the
pin must remain stable for t
arrive at the IOC register.
5V
SK
-t
PK
SPI
-t
IA
indicates that the PCLK signal to the IOC register
). This means that no set-up time for the data
HPI
time, i.e. to wait for the PCLK signal to
A
= 25 C, freq = 25MHZ, V
04-02-052A
CC
=