TSC87C52-12CAB TEMIC [TEMIC Semiconductors], TSC87C52-12CAB Datasheet
TSC87C52-12CAB
Related parts for TSC87C52-12CAB
TSC87C52-12CAB Summary of contents
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... DC, without loss of data. The TSC87C52 retains all the features of the 80C52 with some enhancement bytes of internal code memory (EPROM); 256 bytes of internal data memory (RAM); 32 I/O lines; three 16 bit timers one with count–down and clock– ...
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... TSC87C52 Block Diagram 2 EPROM Figure 1 TSC87C52 Block diagram Preliminary MATRA MHS Rev. C – 10 Sept 1997 ...
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... Flat Pack Figure 2 TSC87C52 pin configuration Preliminary TSC87C52 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA/VPP PLCC/CQPJ 34 Reserved 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 ...
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... DC parameters section) because of the internal pullups. Port 1 can sink/ source three LS TTL inputs. It can drive CMOS inputs without external pullups. Port1 also serves the functions of the following special features of the TSC87C52 as listed below: Port Pin P1 ...
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... Alternate Function RxD (serial input port) TxD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external Data Memory write strobe) RD (external Data Memory read strobe) . The port pins will be driven to their reset CC Preliminary TSC87C52 5 ...
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... ONCE Mode The ONCE mode facilitates testing and debugging of systems using TSC87C52 without the TSC87C52 having to be removed from the circuit. The ONCE mode is invoked by driving certain pins of the TSC87C52, the following sequence must be exercised. Pull ALE low while the device is in reset (RST high) and PSEN is high. ...
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... While the TSC87C52 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 2 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 2 External pin status during ONCE mode ALE PSEN Weak pull–up Weak pull– ...
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... TSC87C52 When in mode 2 and 3 (9–bit mode), RI flag is set during stop bit if framing error is enabled or during ninth bit if not (see Figure 5). SM0/FE SMOD1 SMOD0 Figure 3 Framing error block diagram RXD Start bit RI SMOD0=X FE SMOD0=1 Figure 4 Enhanced UART timing diagram in mode 1 RXD ...
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... Clear to acknowledge interrupt. The reset value of SCON is 0000 0000b. Timer 2 The Timer 2 in the TSC87C52 operates identically to the Timer 2 in the 80C52 but includes the following enhancements. For a complete understanding of the TSC87C52 Timer 2 please refer to the description in the 80C51 Hardware Description Guide. ...
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... TSC87C52 Programmable Clock Output A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input external clock for Timer/Counter output a 50% duty cycle 18 clock from frequency fosc/2 to frequency fosc/4 ( MHz MHz operating frequency). ...
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... This will ensure program protection. EPROM Programming Set–up modes In order to program and verify the EPROM or to read the signature bytes, the TSC87C52 is placed in specific set–up modes (see Figure 8). Control and program signals must be held at the levels indicated in Table 6. ...
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... Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the TSC87C52. To verify the TSC87C52 code the following sequence must be exercised : Step 1: Activate the combination of program signals. Step 2: Input the valid address on the address lines. ...
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... MATRA MHS Rev. C – 10 Sept 1997 Read/Verify Cycle Data In 100us 10us Contents 58h Customer selection byte: TEMIC 58h Family selection byte: C51 ADh TSC87C52 XXh Product revision number 2 Preliminary TSC87C52 Data Out Comment rating for 30 minutes distance of 13 ...
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... TSC87C52 Electrical Characteristics (1) Absolute Maximum Ratings Ambiant Temperature Under Bias commercial . . . . . . . . . . . . . . . . . . . . I = industrial . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . – 150 C Voltage on VCC to VSS . . . . . . . . . . . . Voltage on VPP to VSS . . . . . . . . . . . Voltage on Any Pin to VSS . . . –0 VCC + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . ...
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... VCC – 0.1 0.2 VCC + 0.9 0.7 VCC (6) (6) VCC – 0.3 VCC – 0.7 VCC – 1.5 VCC – 0.3 VCC – 0.7 VCC – 1.5 ( (5) 10 (5) 13@12MHz 16@16MHz 5.5@12MHz 7@16MHz Preliminary TSC87C52 Max Unit Test Conditions V VCC + 0.5 V VCC + 0.5 V (4) 0.3 V IOL = 100 A (4) 0.45 V IOL = 1.6mA (4) IOL = 3.5mA 1.0 V (4) ...
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... TSC87C52 DC Parameters for Low Voltage, commercial and industrial temperature range +70 C; VSS = 0V; VCC = 2. 10 MHz – +85 C; VSS = 0V; VCC = 2. 10 MHz. A Symbol Parameter VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST ...
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... VSS Figure 12 ICC Test Condition, Power Down Mode VCC–0.5V 0.45V TCHCL TCLCH = TCHCL = 5ns. Figure 13 Clock Signal Waveform for ICC Tests in Active and Idle Modes Preliminary TSC87C52 VCC ICC VCC VCC P0 EA All other pins are disconnected. 0.7VCC 0.2VCC–0.1 ...
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... TSC87C52 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. ...
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... TCLCL–50 7TCLCL–150 TCLCL–50 TCLCL–40 TLLWL TWLWH TQVWX TLLAX TQVWH A0–A7 DATA OUT TAVWL ADDRESS A8–A15 OR SFR P2 Preliminary TSC87C52 Units Units Max ns ns 5TCLCL–165 ns ns 2TCLCL–60 ns 8TCLCL–150 ns 9TCLCL–165 ns 3TCLCL+ ...
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... TSC87C52 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR–P2 Serial Port Timing – Shift Register Mode Symbol Symbol Parameter Parameter TXLXL Serial port clock cycle time TQVHX Output data set–up to clock rising edge TXHQX Output data hold after clock rising edge ...
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... Rev. C – 10 Sept 1997 Min 12 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL VERIFICATION ADDRESS ADDRESS DATA OUT DATA IN TGHDX 5 TGHAX Pulses TGHSL TGHGL VPP VCC TELQV Preliminary TSC87C52 Max Units MHz s s 110 s 48 TCLCL 48 TCLCL 48 TCLCL s TAVQV TEHQZ 21 ...
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... TSC87C52 External Clock Drive Characteristics (XTAL1) Symbol Parameter TCLCL Oscillator Period TCHCX High Time TCLCX Low Time TCLCH Rise Time TCHCL Fall Time External Clock Drive Waveforms VCC–0.5V 0.7VCC 0.2VCC–0.1 0.45V TCHCL AC Testing Input/Output Waveforms VCC –0.5 V INPUT/OUTPUT 0. inputs during testing are driven at VCC – 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “ ...
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... DATA PCL OUT SAMPLED FLOAT DATA SAMPLED FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION OLD DATA NEW DATA Preliminary TSC87C52 STATE4 STATE5 DATA PCL OUT SAMPLED FLOAT PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) ...
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... TSC87C52 Ordering Information TSC 87C52 –12: 12 MHz version –16: 16 MHz version –20: 20 MHz version –25: 25 MHz version –33: 33 MHz version –L16: Low Power (VCC: 2.7–5.5V, Freq.: 0–16 MHz) Part Number 87C52: Programmable ROM TEMIC Semiconductor Microcontroller Product Line 24 –20 C OTP Packaging ...