TSC87C52-12CAB TEMIC [TEMIC Semiconductors], TSC87C52-12CAB Datasheet - Page 10

• Manufacturer Part Number: TSC87C52-12CAB
• Description: CMOS 0 to 33 MHz Programmable 8-bit Microcontroller
• Manufacturer: TEMIC [TEMIC Semiconductors]

10
TSC87C52
Programmable Clock Output
alternate functions. It can be programmed to input external clock for Timer/Counter 2 or to output a 50% duty cycle
clock from frequency fosc/2
The clock–out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers
RCAP2H and RCAP2L as shown in this equation:
To configure the Timer/Counter 2 as a clock generator, bit C/T2 in T2CON (bit location 1) must be cleared and bit T2OE
must be set. Bit TR2 in T2CON starts and stops the timer (see Figure 7). T2OE is located in T2MOD at bit location
1 (see Table 5).
In the clock–out mode, Timer 2 roll–overs will not generate an interrupt. This is similar to when Timer 2 is used as
a baud–rate generator. It is possible to use Timer 2 as a baud–rate generator and as clock generator simultaneously.
Note however, that the baud–rate and clock–out frequencies can not be determined independently from one another
since they both use RCAP2H and RCAP2L.
Table 5 T2MOD – Timer 2 Control Register (C9h)
The reset value of T2MOD is XXXX XX00b.
A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two
7
–
Symbol
DCEN
T2OE
–
T2EX
OSC
T2
6
–
C/T2
18
Reserved
Timer 2 Output Enable bit
Decrement Enable bit
to frequency fosc/4 (61 Hz to 4 MHz at a 16 MHz operating frequency).
Do not write 1 in these bits.
Set to program P1.0/T2 as clock output.
Clear to program P1.0/T2 as clock input or I/O port.
Set to enable Timer 2 as up/down counter.
Clear to disable Timer 2 as up/down counter.
Clock–Out frequency=
2
5
–
Figure 7 Timer 2 Clock–Out Mode
Preliminary
4
–
4 (65536 – RCAP2H,RCAP2L)
TR2
EXEN2
Oscillator frequency
2
3
–
Description
RCAP2L
EXF2
(8–bit)
(8–bit)
TL2
2
–
T2OE
RCAP2H
(8–bit)
(8–bit)
TH2
INTERRUPT
T2OE
TIMER 2
1
Rev. C – 10 Sept 1997
OVERFLOW
MATRA MHS
DCEN
0