X4005 XICOR [Xicor Inc.], X4005 Datasheet - Page 9

• Manufacturer Part Number: X4005
• Description: CPU Supervisor
• Manufacturer: XICOR [Xicor Inc.]

X4003/X4005
Serial Read Operations
The read operation allows the master to access the control
register. To conform to the I
the slave address byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the byte address. After acknowledging receipt of the
byte address, the master immediately issues another
start condition and the slave address byte with the R/W
bit set to one. This is followed by an acknowledge from
the device and then by the eight bit control register.
The master terminates the read operation by not
Figure 9. Control Register Read Sequence
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow a write operation.
– The proper clock count and bit sequence is required
– A three step sequence is required before writing into
– The WP pin, when held HIGH, prevents all writes to
– Communication to the device is inhibited below the
– Command to change the control register are termi-
REV 1.1.3 4/30/02
prior to the stop bit in order to start a nonvolatile
write cycle.
the control register to change watchdog timer or
block lock settings.
the control register.
V
nated if in-progress when RESET/RESET go active.
TRIP
voltage.
Signals from
Signals from
the Master
the Slave
SDA Bus
2
C standard, prior to issuing
S
a
r
t
t
1
0
Address
1
Slave
1
0
0
1
0
A
C
K
1
www.xicor.com
1
Address
1
Byte
1
1
1
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 9 for the address,
acknowledge, and data transfer sequences.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
– SDA pin is the input mode.
Symbol Table
1
RESET/RESET signal is active for t
to write to the device.
1
WAVEFORM
C
A
K
S
a
t
r
t
1
0
Address
1
Slave
1
0
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
0
Characteristics subject to change without notice.
1
1
C
A
K
Data
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
PURST
S
o
p
t
.
9 of 18