X5168 INTERSIL [Intersil Corporation], X5168 Datasheet - Page 3
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X5168
Manufacturer Part Number
X5168
Description
CPU Supervisor with 16Kbit SPI EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
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Pin Configuration
Pin Description
(SOIC/PDIP)
PIN
1
2
5
6
3
4
8
7
V
WP
CS
SO
SS
PIN TSSOP
3-5,10-12
8 LD SOIC/PDIP
1
2
3
4
14
13
1
2
8
9
6
7
X5168/69
3
RESET/
RESET
NAME
SCK
V
V
WP
CS
SO
NC
SI
CC
SS
8
7
6
5
Chip Select Input. CS HIGH, deselects the device and the SO output
pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be
in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior
to the start of any operation after power-up, a HIGH to LOW transition on CS is required.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
the minimum V
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
RESET/RESET
SCK
SI
V
CC
CC
X5168, X5169
falls below the minimum V
CC
sense level for 200ms. RESET/RESET goes active if the watchdog timer is
V
NC
NC
NC
CS
SO
WP
SS
14 LD TSSOP
1
2
3
4
5
6
7
CC
FUNCTION
sense level. It will remain active until V
X5168/69
14
13
12
11
10
9
8
NC
NC
NC
RESET/RESET
SCK
SI
V
CC
CC
September 16, 2005
rises above
FN8130.1