M40Z111MH6 STMICROELECTRONICS [STMicroelectronics], M40Z111MH6 Datasheet - Page 7

• Manufacturer Part Number: M40Z111MH6
• Description: 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

OPERATION
The M40Z111/W, as shown in Figure 4, page 4,
can control up to two standard low-power SRAMs.
These SRAMs must be configured to have the
chip enable input disable all other input signals.
Most slow, low-power SRAMs are configured like
this, however many fast SRAMs are not. During
normal operating conditions, the conditioned chip
enable (E
(E) input pin with timing shown in Table 6, page 9.
An internal switch connects V
switch has a voltage drop of less than 0.3V
(I
When V
is forced inactive independent of E. In this situa-
tion, the SRAM is unconditionally write protected
as V
(V
with V
in Table 5, page 6.
Note: The THS pin must be connected to either
V
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
E
ing the SRAM.
A power failure during a write cycle may corrupt
data at the currently addressed location, but does
not jeopardize the rest of the SRAM's contents. At
voltages below V
sured the memory will be write protected provided
the V
As V
disconnects V
to V
(V
age V
I
OUT2
OUT1
SS
CON
PFD
SO
or V
OUT
CC
). Below the V
CC
CC
). The power fail detection value associated
PFD
).
is unconditionally driven high, write protect-
OHB
(see Table 5, page 6). When V
CC
falls below an out-of-tolerance threshold
continues to degrade, the internal switch
. This occurs at the switchover voltage
fall time exceeds t
OUT
CON
is selected by the THS pin and is shown
degrades during a power failure, E
to the SRAM and can supply current
.
) output pin follows the chip enable
CC
and connects the internal battery
PFD
SO
, the battery provides a volt-
(min), the user can be as-
F
.
CC
to V
OUT
CC
. This
rises
CON
WP
,
above V
voltage. Output E
(200ms maximum) after the power supply has
reached V
for processor stabilization (see Figure 7, page 8).
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40Z111/W NVRAM SUPERVI-
SOR. There are, however some criteria which
should be used in making the final choice of which
SRAM to use. The SRAM must be designed in a
way where the chip enable input disables all other
inputs to the SRAM. This allows inputs to the
M40Z111/W and SRAMs to be “Don't Care” once
V
also guarantee data retention down to V
The chip enable access time must be sufficient to
meet the system needs with the chip enable prop-
agation delays included. If the SRAM includes a
second chip enable pin (E2), this pin should be
tied to V
parameter for the system, it is important to review
the data retention current specifications for the
particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0V.
Manufacturers generally specify a typical condi-
tion for room temperature along with a worst case
condition (generally at elevated temperatures).
The system level requirements will determine the
choice of which value to use. The data retention
current value of the SRAMs can then be added to
the I
the total current requirements for data retention.
The available battery capacity for the SNAPHAT
of your choice can then be divided by this current
to determine the amount of data retention avail-
able (see Table 8, page 10). For more information
on Battery Storage Life refer to the Application
Note AN1012.
CC
CCDR
falls below V
SO
OUT
PFD
value of the M40Z111/W to determine
, V
. If data retention lifetime is a critical
, independent of the E input, to allow
OUT
is switched back to the supply
PFD
CON
(min). The SRAM should
M40Z111, M40Z111W
is held inactive for t
CC
= 2.0V.
7/15
ER
®