M40Z111WMH6F STMICROELECTRONICS [STMicroelectronics], M40Z111WMH6F Datasheet - Page 8

• Manufacturer Part Number: M40Z111WMH6F
• Description: 5V or 3V NVRAM supervisor for up to two LPSRAMs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

2
Note:
2.1
8/21
Operation
The M40Z111/W, as shown in
SRAMs. These SRAMs must be configured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are configured like this, however many fast
SRAMs are not. During normal operating conditions, the conditioned chip enable (E
output pin follows the chip enable (E) input pin with timing shown in
internal switch connects V
(I
When V
situation, the SRAM is unconditionally write protected as V
threshold (V
THS pin and is shown in
Note: The THS pin must be connected to either V
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time t
A power failure during a write cycle may corrupt data at the currently addressed location, but
does not jeopardize the rest of the SRAM's contents. At voltages below V
can be assured the memory will be write protected provided the V
As V
battery to V
provides a voltage V
page
E
independent of the E input, to allow for processor stabilization (see
Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM
SUPERVISOR. There are, however some criteria which should be used in making the final
choice of which SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and
SRAMs to be “Don't Care” once V
guarantee data retention down to V
sufficient to meet the system needs with the chip enable propagation delays included. If the
SRAM includes a second chip enable pin (E2), this pin should be tied to V
retention lifetime is a critical parameter for the system, it is important to review the data
retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0V.
Manufacturers generally specify a typical condition for room temperature along with a worst
case condition (generally at elevated temperatures). The system level requirements will
determine the choice of which value to use. The data retention current value of the SRAMs
can then be added to the I
requirements for data retention.
OUT1
CON
CC
14). When V
).
is held inactive for t
continues to degrade, the internal switch disconnects V
CC
degrades during a power failure, E
OUT
PFD
. This occurs at the switchover voltage (V
). The power fail detection value associated with V
CC
OHB
rises above V
WP
to the SRAM and can supply current I
Table 6 on page
ER
, E
CC
CCDR
(200ms maximum) after the power supply has reached V
CON
to V
Figure 3 on page
value of the M40Z111/W to determine the total current
is unconditionally driven high, write protecting the SRAM.
OUT
CC
SO
CC
. This switch has a voltage drop of less than 0.3V
falls below V
, V
= 2.0V. The chip enable access time must be
OUT
14.
is switched back to the supply voltage. Output
CON
7, can control up to two standard low-power
is forced inactive independent of E. In this
SS
PFD
or V
(min). The SRAM should also
SO
OUT
CC
). Below the V
.
falls below an out-of-tolerance
CC
OUT2
CC
and connects the internal
PFD
Figure 5 on page
Table 2 on page
(see
fall time exceeds t
is selected by the
PFD
SO
Table 6 on
OUT
, the battery
(min), the user
. If data
CON
10. An
9).
PFD
F
)
.
,