ATA5811_06 ATMEL [ATMEL Corporation], ATA5811_06 Datasheet - Page 41

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ATA5811_06

Manufacturer Part Number
ATA5811_06
Description
UHF ASK/FSK TRANSCEIVER
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
9.4
Figure 9-2.
4689F–RKE–08/06
Pin Tn
(Status register)
DVCC, AVCC
Timing Pin Tn, Status Bit STn
N_RESET
VSOUT
CLK
STn
IRQ
Tn
To switch the transceiver from OFF to Idle mode, pin Tn must set to 0 (maximum 0.2
at least T
N_RESET to low and switches on DVCC, AVCC and the power supply for external devices
VSOUT.
If V
sets the status bit STn to 1 and an interrupt is issued (T
After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is
elapsed the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-
nous the first clock cycle may be incomplete. N_RESET is set to high if V
(typically) and the XTO is settled.
1.5V (typ)
Mode
OFF
V
DVCC
Thres_2
exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and
= 2.38V (typ)
Tn_IRQ
T
Mode
IDLE
Tn_IRQ
(see
Figure
V
Thres_1
9-2). The transceiver recognize the negative edge, sets pin
= 2.3V (typ)
Tn_IRQ
ATA5811/ATA5812
).
VSOUT
exceeds 2.38V
V
VS2
) for
41

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