M40SZ100WMH6E STMICROELECTRONICS [STMicroelectronics], M40SZ100WMH6E Datasheet - Page 9

• Manufacturer Part Number: M40SZ100WMH6E
• Description: 5 V or 3 V NVRAM supervisor for LPSRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M40SZ100Y, M40SZ100W
2
2.1
Operation
The M40SZ100Y/W, as shown in
parallel) standard low-power SRAM. This SRAM must be configured to have the chip enable
input disable all other input signals. Most slow, low-power SRAMs are configured like this,
however many fast SRAMs are not. During normal operating conditions, the conditioned
chip enable (E
Table 2 on page
of less than 0.3 V (I
When V
situation, the SRAM is unconditionally write protected as V
threshold (V
V
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time t
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the SRAM's contents. At voltages below V
user can be assured the memory will be write protected within the Write Protect Time (t
provided the V
As V
battery to V
provides a voltage V
page
When V
held inactive for t
independent of the E input, to allow for processor stabilization (see
Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40SZ100Y/W NVRAM
Controller. There are, however some criteria which should be used in making the final
choice of which SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M40SZ100Y/W and
SRAMs to be “Don't care” once V
SRAM should also guarantee data retention down to V
time must be sufficient to meet the system needs with the chip enable propagation delays
included.
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 V. Manufacturers generally specify a typical condition
for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
use. The data retention current value of the SRAMs can then be added to the I
the M40SZ100Y/W to determine the total current requirements for data retention. The
available battery capacity for the SNAPHAT
then be divided by this current to determine the amount of data retention available.
PFD
CC
17).
is shown in
continues to degrade, the internal switch disconnects V
CC
CC
degrades during a power failure, E
rises above V
OUT
PFD
CON
CC
. This occurs at the switchover voltage (V
). For the M40SZ100Y/W the power fail detection value associated with
11. An internal switch connects V
CER
Table 7 on page
fall time does not exceed t
) output pin follows the chip enable (E) input pin with timing shown in
OUT1
OHB
(120ms maximum) after the power supply has reached V
WPT
).
to the SRAM and can supply current I
SO
, E
, V
CON
OUT
Doc ID 7528 Rev 3
CC
Figure 5 on page
17.
is unconditionally driven high, write protecting the SRAM.
is switched back to the supply voltage. Output E
falls below V
®
F
CON
of your choice (see
(see
PFD
CC
is forced inactive independent of E. In this
Table 2 on page
8, can control one (two, if placed in
to V
(min) (see
CC
SO
OUT
= 2.0 V. The chip enable access
CC
). Below the V
. This switch has a voltage drop
falls below an out-of-tolerance
CC
OUT2
Figure 6 on page
Table 13 on page
and connects the internal
Figure 7 on page
11).
(see
SO
Table 7 on
, the battery
PFD
CCDR
PFD
Operation
(min), the
10). The
,
CON
22) can
value of
11).
WPT
is
9/24
)