X5043 XICOR [Xicor Inc.], X5043 Datasheet - Page 7

• Manufacturer Part Number: X5043
• Description: CPU Supervisor with 4K SPI EEPROM
• Manufacturer: XICOR [Xicor Inc.]

X5043/X5045
Table 2. Device Protect Matrix
Figure 6. Read Status Register Sequence
Figure 7. Write Status Register Sequence
Read Memory Array
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
8-bit address. Bit 3 of the READ instruction selects the
upper or lower half of the device. After the READ
opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO line. The data stored in memory at the next
REV 1.1.2 5/29/01
WREN CMD
(WEL)
0
1
x
Device Pin
SCK
SO
CS
SI
SCK
(WP)
CS
SO
x
0
1
SI
High Impedance
High Impedance
0
0
1
Protected Area
Instruction
1
Instruction
2
Protected
Protected
Protected
2
3
3
4
4
www.xicor.com
5
Memory Block
5
6
6
7
7
address can be read sequentially by continuing to pro-
vide clock pulses. The address is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached, the address counter rolls over to address
$000 allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by taking CS
high. Refer to the Read EEPROM Array Sequence
(Figure 8).
MSB
8
7
8
7
Unprotected Area
9
9 10 11 12 13 14
6
6
Protected
Protected
10 11 12 13 14 15
Writable
5
5
Data Out
Data Byte
4
4
3
3
2
Characteristics subject to change without notice.
2
1
1
15
0
0
(BL0, BL1, WD0, WD1)
Status Register
Protected
Protected
Writable
7 of 20