X5043 XICOR [Xicor Inc.], X5043 Datasheet - Page 9

• Manufacturer Part Number: X5043
• Description: CPU Supervisor with 4K SPI EEPROM
• Manufacturer: XICOR [Xicor Inc.]

X5043/X5045
Figure 9. Write Memory Sequence
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
– SO pin is high impedance.
– The Write Enable Latch is reset.
– The Flag Bit is reset.
– Reset Signal is active for t
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an active state and receive an instruction.
SCK
SCK
CS
CS
SI
SI
24 25 26 27 28 29 30 31
7
6
0
5
Data Byte 2
1
Instruction
PURST
4
2
3
.
3
2
4
8
1
9
5
th
0
Bit of Address
6
32 33 34 35 36 37 38 39
7
7
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6
7
8
5
Data Byte 3
6
9
4
8 Bit Address
10
5
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the Write
– CS must come HIGH at the proper clock count in
– Block Protect bits provide additional level of write
– The WP pin LOW blocks nonvolatile write operations.
3
Enable Latch.
order to start a nonvolatile write cycle.
protection for the memory array.
2
12 13 14 15 16 17 18 19 20 21 22 23
3
1
2
0
1
0
6
Characteristics subject to change without notice.
7
5
6
Data Byte N
4
5
3
Data Byte 1
4
2
3
1
2
0
1
0
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