X4163 INTERSIL [Intersil Corporation], X4163 Datasheet - Page 13

• Manufacturer Part Number: X4163
• Description: CPU Supervisor with 16K EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

Figure 15. X4163/5 Addressing
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
– SDA pin is the input mode.
– RESET/RESET Signal is active for t
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
– A three step sequence is required before writing into
– The WP pin, when held HIGH, and WPEN bit at logic
ble to write to the device.
prior to the stop bit in order to start a nonvolatile
write cycle.
the Control Register to change Watchdog Timer or
Block Lock settings.
HIGH will prevent all writes to the Control Register.
13
(X1)
A7
D7
1
0
Device Identifier
(X0)
D6
A6
0
0
Word Address Byte 0 for all options
PURST
(Y5)
D5
A5
Word Address Byte 0–16K
1
0
Low Order Word Address
Data Byte for all options
Slave Address Byte
.
(Y4)
D4
A4
0
0
X4163, X4165
(Y3)
D3
A3
0
0
High Order Word Address
Device Select
A10
(X4)
(Y2)
A2
S1
D2
– Communication to the device is inhibited while
– Block Lock bits can protect sections of the memory
SYMBOL TABLE
RESET/RESET is active and any in-progress com-
munication is terminated.
array from write operations.
WAVEFORM
(X3)
(Y1)
S0
A9
A1
D1
R/W
(X2)
(Y0)
A8
A0
D0
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
April 13, 2005
FN8120.0