AK5702VN AKM [Asahi Kasei Microsystems], AK5702VN Datasheet - Page 22

• Manufacturer Part Number: AK5702VN
• Description: 4-Channel ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

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There are the following five clock modes to interface with external devices (Table 1 and Table 2.)
Note 27. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
Note 28. In case of EXT Master Mode, the register should be set as Figure 64.
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The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK5702 is power-down mode (PDN pin = “L”) and exits reset state, the AK5702 is slave mode. After exiting reset state,
the AK5702 goes to master mode by changing M/S bit = “1”.
When the AK5702 is used by master mode, LRCK and BCLK pins are a floating state until M/S bit becomes “1”. LRCK
and BICK pins of the AK5702 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the
floating state. When PDN pin is “H” and PMVCM bit becomes “L”, LRCK, BCLK pin output “L” or “H”. In this
situation, it is possible to draw the current into pulled-down or pulled-up resister. This current can stop by setting M/S bit
to “0”.
MS0623-E-00
Mode
PLL Master Mode (Note 27)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BCLK pin)
EXT Slave Mode
EXT Master Mode (Note 28)
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK
EXT Slave Mode
EXT Master Mode
or BCLK pin)
System Clock
Master Mode/Slave Mode
clocks are output from MCKO pin when MCKO bit is “1”.
PDN pin
H
H
H
H
L
PMVCM bit
Table 1. Clock Mode Setting (x: Don’t care)
H
H
L
L
L
Table 2. Clock pins state in Clock Mode
MCKO bit
Table 3. Select Master/Salve Mode
OPERATION OVERVIEW
0
1
0
1
0
0
0
M/S bit
H
H
L
L
L
Selected by
Selected by
PMPLL bit
MCKO pin
- 22 -
PS1-0 bits
PS1-0 bits
“L”
“L”
“L”
“L”
“L”
1
1
1
0
0
Master
Master
Mode
Slave
Slave
Slave
PLL3-0 bits
PLL3-0 bits
Selected by
Selected by
Selected by
Selected by
FS1-0 bits
FS1-0 bits
MCKI pin
M/S bit
GND
1
0
0
0
1
Output “L” or “H”
LRCK,BCLK pin
BCKO1-0 bits)
BCKO1-0 bits)
PLL3-0 bits)
(Selected by
PLL3-0 bits
See Table 4
See Table 4
See Table 4
Output
(Selected by
(Selected by
BCLK pin
BCLK pin
BCLK pin
BCLK pin
Input
Input
Input
BCLK pin
BCLK pin
(≥ 32fs)
(≥ 32fs)
x
x
LRCK pin
LRCK pin
LRCK pin
LRCK pin
LRCK pin
LRCK pin
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure
(1fs)
(1fs)
(1fs)
(1fs)
(1fs)
[AK5702]
2007/06