AK5702VN AKM [Asahi Kasei Microsystems], AK5702VN Datasheet - Page 27

• Manufacturer Part Number: AK5702VN
• Description: 4-Channel ADC with PLL & MIC-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

■
When PMPLL bit is “0”, the AK5702 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit
is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), LRCK (fs) and BCLK (≥32fs). The master clock (MCKI) should be synchronized with LRCK.
The phase between these clocks does not matter. The input frequency of MCKI is selected by FS3-0 bits (Table 11).
The external clocks (MCKI, BCLK and LRCK) should always be present whenever the ADC is in operation (PMADAL
bit = “1” or PMADAR bit = “1” or PMADBL bit = “1” or PMADBR bit = “1”). If these clocks are not provided, the
AK5702 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If the external clocks are not present, the ADC should be in the power-down mode (PMADAL= PMADAR =
PMADBL = PMADBR bits = “0”).
MS0623-E-00
EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
Mode
0
1
2
3
4
FS3-2 bits
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
00, 01, 11
00, 01, 11
00, 01, 11
00, 01, 11
10
AK5702
Don’t care
FS1 bit
0
0
1
1
MCKO
MCKI
BCLK
LRCK
SDTOA/B
Figure 23. EXT Slave Mode
Don’t care
FS0 bit
256fs, 512fs or 1024fs
0
1
0
1
- 27 -
≥ 32fs
1fs
MCKI Input
Frequency
1024fs
256fs
512fs
256fs
N/A
MCLK
BCLK
LRCK
SDTI
DSP or μP
Sampling Frequency
7.35kHz ∼ 48kHz
7.35kHz ∼ 13kHz
7.35kHz ∼ 26kHz
7.35kHz ∼ 48kHz
Range
-
(default)
[AK5702]
2007/06