AK4440 AKM [Asahi Kasei Microsystems], AK4440 Datasheet - Page 22

• Manufacturer Part Number: AK4440
• Description: 192kHz 24-Bit 8ch DAC with 2Vrms Output
• Manufacturer: AKM [Asahi Kasei Microsystems]

MS1088-E-01
(2) I
The AK4440 supports the fast-mode I
Figure 22
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data direction
bit (R/W)
CAD0 (device address bit). The bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) set
them. If the slave address match that of the AK4440 and R/W bit is “0”, the AK4440 generates an acknowledge and the
write operation is executed. If R/W bit is “1”, the AK4440 does not answer any acknowledge
The second byte consists of the address for control registers of the AK4440. The format is MSB first, and those most
significant 3-bits are fixed to zeros
MSB first, 8bits
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while
SCL is HIGH defines STOP condition
The AK4440 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4440 generates an acknowledge, and awaits the next data. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits
address counter is incremented by one, and the next data is taken into next address automatically. If the addresses
exceed 03H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will
be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW
condition.
2
C-bus Control Mode (I2C pin = “H”)
shows the data transfer sequence at the I
(Figure
SDA
(Figure
23). The most significant six bits of the slave address are fixed as “001001”. The next one bit is
D7
0
0
25). The AK4440 generates an acknowledge after each byte is received. A data transfer is
S
T
A
R
T
S
Slave
Address
Figure 22. Data transfer sequence at the I
D6
0
0
Figure 25. Byte structure after the second byte
(Figure
2
R/W
(This CAD0 should match with CAD0 pin)
C-bus system (max: 400kHz).
(Figure
A
C
K
Sub
Address(n)
D5
24). Those data after the second byte contain control data. The format is
1
0
Figure 24. The second byte
26).
Figure 23. The first byte
2
C-bus mode. All commands are preceded by a START condition. A
A
C
K
A4
D4
0
- 22 -
Data(n)
(Figure
A3
D3
0
A
C
K
Data(n+1)
28) except for the START and the STOP
2
A2
D2
C-bus mode
1
A
C
K
CAD0
A1
D1
A
C
K
Data(n+x)
(Figure
R/W
A0
D0
(Figure
27).
A
C
K
S
T
O
P
P
26). After the
[AK4440]
2011/03